361 commits

Author	SHA1	Message	Date
taoliug	98cfad26f3	Use new ibex_core_tracer as DUT (#148)	2019-07-11 19:35:47 -07:00
taoliug	b0d2c0ff48	Add support for debug mode and interrupt test (#146)	2019-07-11 11:19:06 -07:00
{“Tao	205db5e6ea	Change return to exit in sim script (fixes #137)	2019-07-11 16:39:02 +01:00
taoliug	b203a0f7c7	Add bash shebang to sim script(fixes #133) (#135)	2019-07-10 23:13:21 -07:00
taoliug	6d09fb1060	Add interrupt agent (#116)	2019-07-01 18:25:37 -07:00
taoliug	2d66834f14	Integrate riscv-dv upstream changes (#107) ... * Remove all local patches * Update google_riscv-dv to 00739df Update code from upstream repository https://github.com/google/riscv- dv to revision 00739df0ec744986934097bebcde3ebf5a4fdf81 * Merge pull request #30 from google/dev (taoliug) * Fix LSF options (Tao Liu) * Refactoring to make extension easier (Tao Liu) * Merge pull request #29 from google/dev (taoliug) * Add a sample program (Tao Liu) * Merge pull request #28 from google/dev (taoliug) * Move riscv_core_setting to a separate folder (Tao Liu) * Merge pull request #27 from google/dev (taoliug) * Add ebreak/wfi test, more regression control (Tao Liu) * Merge pull request #26 from google/dev (taoliug) * Add support for GPR based comparison (Tao Liu) * Add ibex extensions for riscv_dv	2019-07-01 08:59:31 -07:00
Pirmin Vogel	2ed71a499a	Make dummy clock gating module compatible with latch-based reg file ... The latch-based register file needs a clock gating cell that is transparent for the clock enable signal only during the low clock phase.	2019-06-26 14:09:23 +01:00
taoliug	cc8aed4ed2	Fix tcl path (#73)	2019-06-07 15:01:19 -07:00
taoliug	52bc23cc39	Add coverage dump options (#71)	2019-06-07 13:58:06 -07:00
taoliug	50c73dcf58	fix ibex TB top compilation issue (#58)	2019-06-04 10:55:22 -07:00
taoliug	2782ae9677	Add UVM testbench ... This adds a UVM testbench and associated tooling for Ibex. The tooling requires Synopsys VCS to run.	2019-06-03 16:45:00 +01:00