If you just build simple_system a fusesoc line like
fusesoc --cores-root=. run --target=sim --setup \
--build lowrisc:ibex:ibex_simple_system
then the change to ibex_simple_system.sv suffices, but if you
explicitly set a parameter in fusesoc like this:
fusesoc --cores-root=. run --target=sim --setup \
--build lowrisc:ibex:ibex_simple_system \
--RV32M=1
then it overrides the default parameter with a literal 1. We declare
the parameter as an 'int', so I guess that's quite a reasonable
behaviour from fusesoc. Anyway, this check only triggers when a 1-bit
parameter is set with a literal 1, so should be safe. (If you do
something buggy like setting it to 2, it will still moan at you). This
patch adds a waiver file in examples/simple_system that silences the
warning.
This patch also makes the equivalent change to riscv_compliance,
adding a waiver file in dv/riscv_compliance/lint and fixing up the
default parameters.
Also fix a minor nit: if something had gone really weird and we saw
a pass message followed by a fail message, the previous code would
have treated the test as a pass. Now it is treated as a failure.
This is mostly just re-indentation and being explicit about what we're
importing from what module, which allows Python lint tools (flake8 and
similar) to spot when there's a typo in a variable name or similar.
The previous version died with a confusing error if you ran it with no
arguments (because the compulsory input and output file paths are
specified as --option arguments).
I've left the arguments optional, but they now default to
stdin/stdout (which means you can now use this script in a pipe).
I've also reformatted the code I touched to look a little more like
PEP8 Python.
Before this patch, running the Makefile's default target deleted
everything and then ran the whole flow. This sometimes does
unnecessary work (if I've just changed the design, there's no need to
rebuild and re-run the instruction generator). It also definitely
won't work with Make's -j flag, since it depends on the targets being
built in order.
This patch keeps the same stages in the Makefile, but makes each stage
generate a stamp file, adding dependencies between the stages. This
way, you can make a small change to the design and re-run the
simulation without having to generate the random inputs again.
This doesn't make much difference if you're running lots of tests with
no LSF (since VCS is very slow, its runtime for simulation completely
dominates), but it can make a significant difference if you're
debugging a single test, have made a change to the design and want to
re-run.
One significant change is that running 'make' doesn't automatically
delete existing files any more. To make this possible (and useful!),
we generate random data and test results in a directory keyed by the
seed. For example
make SEED=123
will generate results in out/seed-123/regr.log (rather than
out/regr.log as before).
To make sure we rebuild things properly if you change something like
the number of iterations or the tests to run, we dump some variables
describing the mode in which we were running. If these don't match the
nnext time around, we'll rebuild stuff if necessary.
Advanced (or hurried) users of the existing Makefile might have done
things like change the design and then run
make SEED=123 compile rtl_sim
Now, the rtl_sim target depends on its logical dependencies. On the
plus side, this means that you won't accidentally simulate out-of-date
code. On the minus side, cunning tricks to avoid having to re-run
stuff after touching a design file won't work. (If you're feeling
really determined to do something like that, it's still possible with
make -t).
The seed-specific stamp files and dumped Make variables go into
$(OUT-SEED)/.metadata directory, rather than $(OUT-SEED)/instr_gen or
$(OUT-SEED)/rtl_sim. This is because of a review comment (to avoid
extra clutter in the output directories).
The process_regression_list function from riscv-dv is really chatty.
When we're just compiling the testbench, we don't actually need to
figure out what tests we're running, since we'll never run them
anyway. So don't call it.
If VERDI_HOME is not set, calling fsdbDumpfile makes VCS hang with an
error message. This patch checks whether we think FSDB dumping is
actually going to work and, if not, dumps with the default VCD+
format (also called VPD) instead.
This commit modifies the `mip` CSR to not depend on the `mie` CSR. While
the values of both these CSRs are combined to decide whether an
interrupt shall be handled, the RISC-V spec does not state that the
content of of `mip` should depend on `mie`. This commit better aligns
Ibex with other open-source RISC-V cores.
This resolveslowRISC/ibex#567 reported by @pfmooney.
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
In `VerilatorMemUtil::WriteElfToMem`, the verilator memory is written
with the ELF segment data, 4 bytes at a time . If the segment size isn't
a multiple of 4 (e.g. when using the RISC-V C extension) the last word
wouldn't be written. This patch rounds the size up to a multiple of 4,
solving that issue.
Riviera do not support parameters of dynamic/associate/queue array types.
The SV standard does not say explicitly that such code is legal.
IMHO this code is at least controversial as dynamic nature of such array
types are against static nature of parameters. It would be better to change
this "implemented_csr" from parameter to const.
This commit adds the performance monitor counters to the CS register
testbench. Mismatches in `mcycle(h)` are currently being ignored as the
cycle counter is expected to increment with every clock cycle (unless
deactivated).
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
In case one of the arguments is '-h' the parsing of the arguments is
aborted and only `PrintHelp()` of *verilator_sim_ctrl.cc* is executed.
Do not abort at this point in order to forward the arguments to the
registered extensions. This allows to execute the respective
`PrintHelp()` function and print the help message. For example
`VerilatorMemUtil` needs to parse the arguments in order to print the
help message.
The execution of the simulation is still terminated as `exit_app` is set
and then evaluated after parsing of the registered extensions.
As described in https://github.com/lowRISC/opentitan/issues/1245,
the Ibex Verliator ELF processing does not exactly follow the algorithm
for the "binary" target of objcopy (which it is intended to mimic).
In particular, sections as denoted by program headers are laid down
strictly sequentially, ignoring their specified p_paddr -- and
resulting in a corrupted in-memory image for ELF images that have
unordered program headers.
This commit replaces all X assignments in the RTL with defined
values. In addition, SystemVerilog Assertions are added to catch
invalid signal values in simulation. A new file containing the
corresponding assertion macros is added as well.
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
- Add the minimum amount of trigger system to support GDB hbreak
- Only a single trigger is implemented
- Only instruction address matching
- Only break into debug mode (no native debug)
- Fixes#382
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
