The previous code correctly dumped to "waves.fsdb" if you had Verdi
installed. Unfortunately, it dumped to the same file name if you
didn't, which was rather confusing.
This patch passes a "DUMP_BASE" environment variable, rather than
"DUMP_FILE", which doesn't include the extension. Then it appends the
correct extension at runtime in the TCL, when we tell VCS what sort of
dumping to do.
The code now also checks for all environment variables before reading
them, allowing defaults if they don't exist. The defaults might not be
what you want, but a syntax error at this point causes VCS to sit
waiting for terminal input (with no stdin!), which is kind of annoying.
I've also removed the copy-pasted Verdi documentation. Apart from
anything else, this is probably copyright, so we shouldn't have a copy
in the repo!
- Add parameters and actual instantiation of icache
- Add a custom CSR in the M-mode custom RW range to enable the cache
- Wire up the cache invalidation signal to trigger on fence.i
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
The option to limit the verilator simulation's maximum number of cycles was
implemented in terms of the `time_` variable, which counts half cycles. This
patch makes the limit respect the requested number of full cycles.
The patch divides `time_` by 2, instead of multiplying `term_after_cycles_`
by 2, as that better conveys the intended semantics, and slightly increases
the range of the limit. Related computations were modified for consistency.
When we run sim.py, we get commands to run the simulator from the YAML
file named by the --simulator_yaml argument, which defaults to
yaml/rtl_simulation.yaml.
This patch makes the argument explicit in the Makefile and adds a
dependency on that file for commands that read it.
This fixes a bug mentioned in issue #674, where dumped wave files were
ending up in dv/uvm/core_ibex, rather than a test-specific output
directory.
It turns out that this is because of my change in commit 08fc2a4,
which runs the simulator in the top core_ibex directory, rather than
changing directories each time. We have to do this to make the
parallel LSF flow work (which presumably has never actually been run,
otherwise we'd have noticed it was broken).
There are two ways I can think of getting this to work. Probably the
cleanest approach is to generate a script for each test, which looks
something like "cd test_dir; setup_stuff; run_simulator". This would
work (and is how I've seen it done in the past), but doesn't really
fit in with the string interpolation/YAML stuff we've got here.
Instead, this patch goes for a hackier approach, where we prefix the
simulation command with "env SIM_DIR=<out>" and then use the SIM_DIR
environment variable in the TCL scripts to figure out where to put the
wave file. This is kind of icky long-term, but should work for now.
I've also got rid of the code that appends some extra plusargs and a
log argument to the simulation command; now, the relevant variables
get substituted in and the actual command is found in
rtl_simulation.yaml.
For packed structs used as input/output port, Questa reports
"Defaulting port 'irqs_i' kind to 'var' rather than 'wire'
due to default compile option setting of -svinputport=relaxed."
The relevant help message says:
```
verror 13314:
vlog Message # 13314:
An input port that is declared with a type but without the 'var' keyword
should default to 'wire' for strict LRM conformance. The default compile
option of -svinputport=relaxed is not LRM compliant, and only defaults
4-state scalar or 4-state single dimension vector types to 'wire'.
Consider using -svinputport=net for strict conformance. See the vlog -help
text for other behaviors available with the -svinputport option.
```
In our code base we can rely on the LRM-compliant handling of this
construct and opt into that using `-svinputport=net`.
Fixes#670
This adds a dependency on $(TESTLIST) (which is that file) for each
target that depends on $(TEST_OPTS), a set of command line options
that includes --testlist=$(TESTLIST).
In practice, we could actually just add the dependency to the
$(metadata)/instr_gen.gen.stamp target, since all the other affected
targets transitively depend on that, but this seems a little confusing
so I've made the dependency explicit.
This is mostly just adding comments and docstrings and pulling the
guts of the comparison into its own function.
I've also got rid of the subprocess calls for appending to a log file
and now calculate the pass/fail count from the return codes of the
checkers rather than grepping in the regression log (hopefully it
gives the same result!)
Since we're not doing stuff with 'make -f path/to/Makefile', we always
know that DV_DIR (as computed) is the current directory, so we can get
rid of it completely.
This is a bit more verbose, but I think it's a bit more obvious what's
going on, and quite a lot of the added lines are docstrings explaining
the code.
We now split "find the list of commands to run" from "run the
commands" with or without LSF.
The other major change is that the --lsf_cmd parameter defaults to
None, rather than the empty string. The patch also updates the
Makefile accordingly.
Finally, since we're now a little more careful with passing paths
around, we don't have to change cwd for each run. I'm not convinced
that the LSF mode actually worked before, since we needed to run each
command in a different directory. It should probably work now, but I
don't have access to LSF to check.
The only sad thing is that UVM leaves a 'tr_db.log' file lying around
in the current directory. I don't think we really care about the
contents, but can't see how to disable it, so I've added it to
gitignore.
Before this patch, the default behaviour picked a different random
seed for each test run (and didn't store it anywhere). I think this is
a bit confusing: you can't reproduce the test without digging around
in log files. Now, we pick a seed at the start of the program, print
it, and use it for each test (not as crazy as this sounds: the seed
controls things like random stalls, but the tested program will be
different each time).
Note that this patch won't actually have any effect, since we
currently only use sim.py from dv/uvm/core_ibex/Makefile, which
specifies the seed every time.
Since these are boolean flags "enable this, please", we use argparse's
support for them.
Command line change:
Before: --en_cov=0
After:
Before: --en_cov=1
After: --en_cov
and similar for en_wave
This generally tidies up and documents how we substitute options and
environment variables in get_simulator_cmd. It's now slightly laxer,
so it won't moan about a missing environment variable or option if
it's not actually used in the command.
This means we can wrap main() in a try/except block. That way, future
patches can change code that fails to throw an exception, rather than
having to do the ugly "write to stderr; exit 1" dance.
This also catches a global (cwd) which we were passing implicitly to
rtl_sim. Fortunately, we already have that value in _CORE_IBEX, so can
just use that.
We now put sys.path back after importing things and no longer import
'*' from anything (which means static analysis tools can now spot when
we've got a name wrong).
The third pipeline stage is a new writeback stage. Ibex can now be
configured as the original two stage design or the new three stage
design using the `WritebackStage` parameter in ibex_core. This defaults
to 0 (giving the original two stage design).
The three stage design is *EXPERIMENTAL*
In the three stage design all register write back occurs in the third,
final stage. This allows a cycle for responses to loads and stores so
when the memory system can respond in a single cycle there will be no
stall. This offers significant performance benefits.
Documentation of the three stage design is still to be written so
existing documentation applies to the two stage design only as various
aspects of Ibex behaviour will change in the three stage design.
Signed-off-by: Greg Chadwick <gac@lowrisc.org>
The --end_signature_addr argument doesn't go to Verilog; instead it
makes it through run.py (vendored-in, so hard to change) and
eventually gets inserted into some assembly code.
Before this patch,
make ITERATIONS=1 TEST=riscv_csr_test ISS=spike SEED=123
failed with:
out/seed-123/instr_gen/asm_tests/riscv_csr_test_0.S: Assembler messages:
out/seed-123/instr_gen/asm_tests/riscv_csr_test_0.S:526: Error: illegal operands `li x2,8ffffffc'
out/seed-123/instr_gen/asm_tests/riscv_csr_test_0.S:533: Error: illegal operands `li x2,8ffffffc'
We do this by pulling the definition of host_addr_o and host_req_o out
of an always_comb process in riscv_testutil.sv.
When set inside the process, Verilator warns about a combinatorial
loop. This happens because a read request could go out on the bus and
appear again (combinatorially) on the slave interface, setting
read_signature_and_terminate. This doesn't actually happen (because
read_signature_and_terminate only takes effect when we are in state
WAIT), but Verilator's sensitivity tracking isn't fine-grained enough
to notice.
