5 commits

Author	SHA1	Message	Date
Tom Roberts	aae437d75b	[rtl] Add alert outputs ... - Add a major and minor alert output which can be used by the system to react to fault injection attacks Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>	2020-07-15 09:50:23 +01:00
Philipp Wagner	f98ddabee1	Use the Xilinx primitives for the Arty board ... Use Xilinx-specific implementations for primitives, such as RAM and the clock gate (which will now be implemented using a BUFGCE macro, and no longer with a latch). Verified in Vivado synthesis to pick up the Xilinx primitive now.	2020-07-06 10:20:39 +01:00
Rupert Swarbrick	006617f95a	Fix SRAM initialisation for fpga/artya example ... This now gets passed to the underlying primitive as a parameter (instead of a define).	2020-07-03 16:06:48 +01:00
Noam Gallmann	11a5fc24d4	Merge pull request #624 from ganoam/fpga-opt-perf-mon-pr ... Modifiy Performance Counter for DSP Inference	2020-03-06 12:49:51 +01:00
Stefan Tauner	0f0571f0ee	FPGA example: add support for the Arty A7-35	2020-01-27 20:18:17 +00:00