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Author SHA1 Message Date
Markus Wegmann
f2a673c3fb Fix wrong support region for bit count operations 2016-12-09 20:09:09 +01:00
Markus Wegmann
87045fc1a6 Fix bug in ALU concerning adder and rounding introduced by false commenting 2016-12-09 20:01:28 +01:00
Markus Wegmann
a6aa948a96 Remove bit operations from result mux in ALU 2016-12-09 16:19:20 +01:00
Markus Wegmann
763e535867 Remove bit masking from ALU 2016-12-09 15:24:28 +01:00
Markus Wegmann
400f0867d9 Add clip operations to special math support. 
Also add normalization to bit support
 2016-12-08 12:31:29 +01:00
Markus Wegmann
6a969e6431 Merge in all changes from RI5CY core 2016-12-07 13:36:44 +01:00
Markus Wegmann
83f1071356 Possibly fix last 2016-12-02 17:20:19 +01:00
Markus Wegmann
0f74c425ad Potentially fix LS instruction bug introduced with last commit 2016-12-02 11:58:31 +01:00
Markus Wegmann
5307658e69 Remove HWLP signals from core.sv 2016-12-01 20:43:28 +01:00
Markus Wegmann
6432e4b051 Remove PrePost Increment. Remove scalar replication signal. 2016-12-01 17:03:19 +01:00
Markus Wegmann
0cc959be74 Rename two-port register file mode 2016-12-01 13:27:17 +01:00
Markus Wegmann
e978cce450 Fix potential bug with ALU opcode not being set when disabling multiplier 2016-12-01 12:58:07 +01:00
Pasquale Davide Schiavone
dd3a816c54 removed comments 2016-11-29 15:55:39 +01:00
Markus Wegmann
b40d3848bc Fix typo in config region 2016-11-29 10:46:33 +01:00
Markus Wegmann
72d4f0e81f Fix syntax to be configurable as full RI5CY 2016-11-28 18:12:11 +01:00
Markus Wegmann
adb58c4cb7 Fix merge typo 2016-11-28 17:02:37 +01:00
Markus Wegmann
9e92b24551 Merge RI5CY master 2016-11-22 11:14:36 +01:00
Markus Wegmann
b0be60b04a Fix syntax in simplified ALU 2016-10-31 07:08:34 -04:00
Markus Wegmann
2062d3274e Add alu_simplified.sv to src files. 2016-10-21 10:01:05 +02:00
Markus Wegmann
bd48b97ffb Fix syntax in riscv config 2016-10-20 22:19:39 +02:00
Markus Wegmann
64d80a79e1 Remove special math and bit operations 2016-10-20 22:06:52 +02:00
Markus Wegmann
5445d0a08e Add simplified ALU 2016-10-20 17:17:59 +02:00
Markus Wegmann
99b1849f54 Fix last 2016-10-18 15:34:57 +02:00
Markus Wegmann
89cb4a7b7e Fix last commit 2016-10-18 15:30:35 +02:00
Markus Wegmann
8dad2dce56 Fix wrong assertion due to removing hardware loop support 2016-10-18 15:27:34 +02:00
Markus Wegmann
5caf622c3c Fix wrong syntax in prefetch buffer due to removal of hardware loop 2016-10-18 15:24:05 +02:00
Markus Wegmann
2d0152afe9 Fix missing parameter due to removing of hardware loop 2016-10-18 15:17:08 +02:00
Markus Wegmann
942d5944f7 Remove Hardware Loop 2016-10-18 15:04:28 +02:00
Markus Wegmann
f5fc141ce4 Add switch for Vector support. Remove divider when multiplier removed. 2016-10-17 18:09:04 +02:00
Pasquale Davide Schiavone
7c5dff2cc5 Small fix in exc controller 2016-10-17 13:12:36 +02:00
Markus Wegmann
acb09458f7 Add missing MUL_SUPPORT region 2016-10-17 11:57:21 +02:00
Markus Wegmann
2d5f2365c1 Fix MUL_SUPPORT section in controller 2016-10-17 11:54:29 +02:00
Markus Wegmann
783eeb6172 Add missing MUL_SUPPORT directives 2016-10-17 11:51:41 +02:00
Markus Wegmann
bd0728a8d9 Add missing whitespace in ALU module (coding convention) 2016-10-17 11:04:30 +02:00
Markus Wegmann
fbc5c074bc Add RI32M support switch and apply it to all signals 2016-10-17 11:04:00 +02:00
Markus Wegmann
6b42805ee7 Add missing whitespace in section title of multiplier module 2016-10-17 11:02:19 +02:00
Markus Wegmann
16a5f9fb11 Revert "Remove most custom ISA instructions from decoder." 
This reverts commit 5f4989d9cb.

Revert uncommenting the decoder commands to begin with the ALU
 2016-10-17 09:35:43 +02:00
Pasquale Davide Schiavone
7e9c374461 small fix in lsu but not tested yet because data_err is not connected to the system 2016-10-14 11:13:20 +02:00
Pasquale Davide Schiavone
8e452c3395 Fixed external interrupt request during invalid instruction 2016-10-13 14:40:46 +02:00
Pasquale Davide Schiavone
3f3f9924a1 Merge branch 'master' of iis-git.ee.ethz.ch:pulp-project/riscv 2016-10-12 09:03:51 +02:00
Pasquale Davide Schiavone
c2a69926b3 Added clip, addsubnorm and bitman reg variant instructions 2016-10-12 09:02:47 +02:00
Pasquale Davide Schiavone
5e2c0fb2ad Merge branch 'typo-readme' into 'master' 
Fix typo in readme

/cc @pasquale.schiavone 

See merge request !9
 2016-10-09 11:42:00 +02:00
Robert Schilling
3e645bd1dd Fix typo in readme 2016-10-07 13:00:11 +02:00
Markus Wegmann
5f4989d9cb Remove most custom ISA instructions from decoder. 2016-10-04 15:03:29 +02:00
Pasquale Davide Schiavone
557f18151c Merge branch 'fix-typos' into 'master' 
Fix some typos

/cc @pasquale.schiavone 

See merge request !8
 2016-09-05 09:52:38 +02:00
Robert Schilling
63666b3105 Fix some typos 2016-09-02 09:22:33 +02:00
Pasquale Davide Schiavone
5338cc01a4 Optimized Clip in ALU and removed trilling white spaces in prefetch_L0_buffer 2016-07-29 10:46:40 +02:00
Pasquale Davide Schiavone
3e1a7b8f45 Optimized shifter in ALU 2016-07-29 09:38:57 +02:00
IGOR LOI
dc7c02a164 updated prefetch buffer, removed bubbles for misaligned 32b instructions during crossword 2016-07-19 18:01:18 +02:00
Pasquale Davide Schiavone
92ae281aab Implemented beqimm and bneimm 2016-07-06 11:39:28 +02:00