Commit graph

846 commits

Author SHA1 Message Date
taoliug
7280301369
Fix ELF section name (#314) 2019-09-13 16:11:41 -07:00
taoliug
54eb5c2456
Fix regression failure (#313) 2019-09-13 16:02:34 -07:00
Philipp Wagner
6b03bc6326 Run clang-format on all source files 2019-09-11 12:00:49 +01:00
udinator
ac22439374
Update slave_driver grant timing to pass Ibex assertion checks (#295) 2019-09-09 14:31:29 -07:00
Greg Chadwick
bec84ca2b1 Add core_sleep_o to ibex interface
Signals the core is totally idle (WFI with no outstanding memory
transactions).  Fixes #258
2019-09-06 08:44:48 +01:00
udinator
e9c2b2ecb3
Added dret and ebreak tests (#281) 2019-09-04 16:14:41 -07:00
Greg Chadwick
d14312c3cc Replace cluster_id/core_id with hart_id (#29)
If you're migrating from the previous interface you can use

logic [31:0] hart_id;
assign hart_id = {21'b0, cluster_id_i[5:0], 1'b0, core_id_i[3:0]};

...

ibex_core #(
  ...
) u_core (
  ...

  // replace core_id_i and cluster_id_i
  .hart_id_i(hart_id),

  ...
);
2019-09-03 14:18:39 +01:00
udinator
68b170638a
Update interrupt mode, add debug mode WFI test (#268) 2019-08-28 10:00:36 -07:00
udinator
2421472395
Integrate risc-v stream generator handshake into Ibex sim flow (#264) 2019-08-26 15:18:30 -07:00
Philipp Wagner
399f0b7e77 Update documentation how to run riscv-compliance
Upstream has now included ibex support, we don't need to use a custom
fork any more. Update the documentation for that.

Fixes #214
2019-08-22 23:27:13 +01:00
taoliug
03df591266
Make mtvec writable, remove previous workaround (#256) 2019-08-21 18:16:51 -07:00
taoliug
2601e8d898
Test cleanup (#255) 2019-08-21 17:19:16 -07:00
udinator
9311b25fdb
Consolidate some debug generation options, and make the signature_addr handshake optional (#253) 2019-08-21 11:00:17 -07:00
udinator
3bc83365ef
Add more debug tests (#251) 2019-08-20 11:03:15 -07:00
udinator
e4260dd075
Add basic debug test and modify sim flow (#243) 2019-08-15 11:18:07 -07:00
taoliug
0e91a30496 [DV] Enable aligned load/store test (#242)
* Add unaligned load/store test

* Enable unaligned load/store test, remove obsolete files
2019-08-14 17:41:13 -07:00
taoliug
9309621f04 Fix the verbose logging issue, fix coverage/waveform options (#235) 2019-08-13 10:23:07 -07:00
udinator
9a231c9ba6
update ibex testbench (#232) 2019-08-12 13:14:07 -07:00
udinator
27bd4e73d9 update ibex simulation flow (#233) 2019-08-09 15:49:46 -07:00
Tom Roberts
44b033cf8b [rtl] Add support for instruction fetch errors
- Add required signals to top-level
- Propagate error through fetch stages
- Add new exception type
- Update documentation for new exception type
- Resolves issue #109
2019-08-09 10:44:37 +01:00
Philipp Wagner
e5bdf1ea9f Document register map of compliance test system 2019-08-06 11:48:50 +01:00
taoliug
50f8cbd463 Fix waveform/coverage dump mode (#215) 2019-08-05 14:42:00 -07:00
Philipp Wagner
24a9c64bf1 Add simulation for RISC-V compliance testing
This adds a Verilator simulation of Ibex for use in RISC-V Compliance
Testing. In addition to ibex itself, the simulation contains a RAM and
a memory-mapped helper module for the test software to interact with the
outside world. The test framework uses this to dump a "test signature",
which is written to a certain part of the memory, and to end the
simulation. (In the future, this could be extended to include printf()
like functionality.)
2019-08-05 15:49:15 +01:00
Philipp Wagner
b72f5db6bd DV: Add verilator simulation utility 2019-08-05 15:49:15 +01:00
taoliug
54fac2954a
Move DV README.md to doc/verification.rst (#208) 2019-08-02 15:05:02 -07:00
taoliug
584ceda381 Add README.md for the DV flow (#207) 2019-08-02 13:45:33 -07:00
taoliug
463f518424 Integrate with new end-to-end simulation (#206) 2019-08-02 08:31:12 -07:00
taoliug
511b205226
Enable WFI test in regression (#190) 2019-07-24 13:52:00 -07:00
taoliug
2bf1ab923a
Fix interrtup test (#189)
Update TB for the new interrupt interface
2019-07-24 11:46:18 -07:00
Pirmin Vogel
72c77f855d Remove legacy interrupt controller
This removal got partially lost while rebasing for PR #149.
2019-07-24 15:57:36 +01:00
Philipp Wagner
62f3573f2b Rework how tracer is instantiated and called
This change is slighly painful, but a necessary cleanup around the
tracer.

- We now provide a separate core file for the tracer, called
  "ibex_tracer.core" (in line with "ibex_tracer.sv"). The core is called
  "lowrisc:ibex:ibex_tracer".
- The toplevel wrapper with tracing enabled got renamed to
  "ibex_core_tracing.sv", and the core file is correspondingly called
  "ibex_core_tracing.core. The core in it is called
  "lowrisc:ibex:ibex_core_tracing".
- Finally to keep symmetry, the toplevel of Ibex itself got renamed in
  the core file from "lowrisc:ibex:ibex" to "lowrisc:ibex:ibex_core".
  This ensures that we have the same name for the core file, the source
  entry point, and the core name.

IMPORTANT NOTE:
If you apply this change and use fusesoc, you need to adjust the name of
the core dependency from "lowrisc:ibex:ibex" to
"lowrisc:ibex:ibex_core".
2019-07-23 19:45:48 +01:00
taoliug
bc61f0bfd9
Fix compile issue caused by design changes (#179) 2019-07-19 18:01:12 -07:00
taoliug
c96ece0429
fix ibex regression script (#165) 2019-07-16 17:56:39 -07:00
taoliug
30f2d6db64
debug mode related TB updates (#160) 2019-07-15 16:36:18 -07:00
taoliug
4eaa57041d
fix debug_seq runtime options, update trace processing script (#158) 2019-07-15 13:25:15 -07:00
taoliug
98cfad26f3
Use new ibex_core_tracer as DUT (#148) 2019-07-11 19:35:47 -07:00
taoliug
b0d2c0ff48
Add support for debug mode and interrupt test (#146) 2019-07-11 11:19:06 -07:00
{“Tao
205db5e6ea Change return to exit in sim script (fixes #137) 2019-07-11 16:39:02 +01:00
taoliug
b203a0f7c7
Add bash shebang to sim script(fixes #133) (#135) 2019-07-10 23:13:21 -07:00
taoliug
6d09fb1060
Add interrupt agent (#116) 2019-07-01 18:25:37 -07:00
taoliug
2d66834f14
Integrate riscv-dv upstream changes (#107)
* Remove all local patches

* Update google_riscv-dv to 00739df

Update code from upstream repository https://github.com/google/riscv-
dv to revision 00739df0ec744986934097bebcde3ebf5a4fdf81

* Merge pull request #30 from google/dev (taoliug)
* Fix LSF options (Tao Liu)
* Refactoring to make extension easier (Tao Liu)
* Merge pull request #29 from google/dev (taoliug)
* Add a sample program (Tao Liu)
* Merge pull request #28 from google/dev (taoliug)
* Move riscv_core_setting to a separate folder (Tao Liu)
* Merge pull request #27 from google/dev (taoliug)
* Add ebreak/wfi test, more regression control (Tao Liu)
* Merge pull request #26 from google/dev (taoliug)
* Add support for GPR based comparison (Tao Liu)

* Add ibex extensions for riscv_dv
2019-07-01 08:59:31 -07:00
Pirmin Vogel
2ed71a499a Make dummy clock gating module compatible with latch-based reg file
The latch-based register file needs a clock gating cell that is
transparent for the clock enable signal only during the low clock
phase.
2019-06-26 14:09:23 +01:00
taoliug
cc8aed4ed2
Fix tcl path (#73) 2019-06-07 15:01:19 -07:00
taoliug
52bc23cc39
Add coverage dump options (#71) 2019-06-07 13:58:06 -07:00
taoliug
50c73dcf58
fix ibex TB top compilation issue (#58) 2019-06-04 10:55:22 -07:00
taoliug
2782ae9677 Add UVM testbench
This adds a UVM testbench and associated tooling for Ibex. 
The tooling requires Synopsys VCS to run.
2019-06-03 16:45:00 +01:00