It turns out that there aren't many changes needed, but we need to be
able to point at a prim directory that might not be inside
vendor/lowrisc_ip: put that path in an environment variable and pass
it from core_ibex/Makefile. That way, a caller on the OpenTitan side
can just override the corresponding variable and everything works.
Commit f49f452f2 greatly tidied up the file, which is nice, but also
introduced some whitespace around the first argument to vars-prereq.
In Make, this causes chaos!
In particular, we ended up checking whether a variable called
something like "$(last- gen -vars-loaded)" was defined. It isn't,
but $(last-gen-vars-loaded) is.
Call strip in the vars-prereq function to get rid of the whitespace at
the "entry point" for all this machinery.
This is the first such script, but the idea is that we're going to
move a bunch of logic out of the Makefile and into Python scripts
where things are a bit easier to understand.
This isn't supposed to be something that people update manually.
Remove it from instr-gen-build-var-deps, since it's not something that
should ever change under our feet.
We're not using this and I strongly doubt that it actually works. Drop
the technical debt: we can always put something back in if we need to
in future.
Some commands utilise a logfile argument, while others capture the stdstreams
into a file. Discard the stdout/stderr when a logfile argument is used.
This keeps the logs readable.
This commmit enables parallelism of more steps of the dv process by capturing
the commands generated by the riscv-dv tool, then populating and executing a
sub-makefile. This allows us to have parallelism at the level of the makefile
jobserver.
Seperated instr_gen build and run steps
A python script construct_makefile.py is used to capture the raw output commands
and construct a trivial makefile for each stage.
This commit also renames some of the helper variables and stamps for consistency.
- Every line in a recipe must start with a tab, except wrapping lines of dependencies.
- Wrapping dependencies of a target use only spaces. Use two spaces by default.
Vivado gives synthesis error complaining about assignment of irq_nm_int_cause to '0 by saying it is an enum type.
Change the assignment to NMI_INT_CAUSE_ECC, which is defined to 5'b0 in ibex_pkg.sv
The prefetch buffer and icache both treat the branch_i and
branch_mispredict_i signals identically, so it's a bit cleaner to pull
that treatment up into ibex_if_stage.sv
This commit doesn't change the modules below: it just passes zeros for
the "mispredict" version. Removing those ports will be done in a
follow-up commit.
An internal interrupt triggers an NMI. A single one is implemented, one
on integrity errors being seen in load data. This replaces a synchronous
exception on an integrity error which caused timing issues.
It turned out that with the default value of 1, Vivado infers a separate
18 Kbit BRAM instance for each bit of the 32-bit word for the FPGA
examples. This can be very wasteful in terms of resource utilization
especially for smaller configurations.
As our examples don't use ECC or parity and mainly target simualation
and FPGA, it's better to use a value of 8 for the DataBitsPerMask
parameter. Vivado will then not distribute words across different BRAM
instances which results in more efficient FPGA resource utilization.
For a detailed analysis and explanation, please refer to
lowRISC/Ibex#1587.
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
Update code from upstream repository https://github.com/google/riscv-
dv to revision cb4295f9ce5da2881d7746015a6105adb8f09071
* Update list search (Matthew Ballance)
* Trap and report exceptions encountered in sub-processes and
propagate error back (Matthew Ballance)
* Workaround fix for loop test colon issue (aneels3)
* Fix typo (aneels3)
* Add support for RV64AFD (aneels3)
* Fix typo (aneels3)
* Update README.md (aneels3)
* Add support for sub_programs (aneels3)
* fix issue with imm value for 64 bit instr (aneels3)
* Allow for underscores and capital letters in ISA for ISS (Pirmin
Vogel)
* implement rv64i (shrujal20)
* Add support for RV32FD coverage (aneels3)
* Integrate random seed for pyflow (aneels3)
* Add riscv_loop_test (ShraddhaDevaiya)
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
This is necessary for having VCS support with simple system example.
Because in the ibex_simple_system_main.cc we are including some
Verilator exclusive header files.
Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
This commit adds ibex_icache_ram_if to connect between DUT and tag /
data RAMs.
This interface injects 1 or 2 bit error on rdata if enable_ecc_errors
bit is set. It also checks that ecc_err_o pin is asserted by DUT
whenever an ecc error is injected.
ibex_icache_ecc_vseq and ibex_icache_base_vseq have been modified to
inject ecc errors through the ram interface.
Fixes a bug where both Xcelium and Python open the same sim.log file and race to
write the simulation results into it. This change makes Python the sole writer of this
file using the captured stdout/stderr from the subprocess.run call in
run_rtl.py.
This bug was also previously present for VCS but was fixed in 90ff7ca6c.
