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Author SHA1 Message Date
Greg Chadwick
c0f67946f2 [rtl,doc] Add double fault detection. 
Fixes #1117
 2022-01-25 15:05:39 +00:00
Greg Chadwick
97fa5cf280 [rtl,doc] Add customisable PMP reset values 
Fixes #1423
 2022-01-24 10:01:36 +00:00
Srikrishna Iyer
7c7e0e6d70 [ibex_tracer] Void cast function calls 
...whose return value is ignored. This cleans up a compile time warning.

Signed-off-by: Srikrishna Iyer <sriyer@google.com>
 2022-01-20 16:59:22 -08:00
Canberk Topal
187944c417 [icache] Add RAM Primitives for scrambling 
This commit includes switching to a scrambling RAM primitive for
ICache data and tag RAMs. Also introduces minor changes to ICache
to handle scrambling key valid signal.

It also includes a minor bug fix regarding not initializing
`fill_way_q` signal without ResetAll parameter. When the parameter
is not set and we have our first hit right after ICache enables,
the signal hangs.

Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
 2022-01-19 14:59:43 +00:00
Greg Chadwick
e53b033962 [examples/fpga] Fix memory interface 
Logic driving instr_gnt/data_gnt violated Ibex memory protocol. It just
happened to work until a recent change.

Fixes #1500
 2022-01-14 09:00:48 +00:00
Greg Chadwick
2ec8d7433e [examples/fpga] Use 64 kB memory by default 
The 256 kB is too large for the Arty-A7 with the A7-35T. Only use it
for the FPGA power analysis configuration.
 2022-01-14 09:00:48 +00:00
Greg Chadwick
dcdd982686 [lint] Lint fix for RndCntLfsrX parameters 
This doesn't produce a lint warning in the version of verilator
currently used in CI but does produce a warning in newer versions.
 2022-01-14 09:00:48 +00:00
Pirmin Vogel
448191dda2 [rtl] Use prim_flop/clock_mux2 primitives for lockstep reset generation 
These primitives can serve as anchor points for constraining backend
tools.

Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
 2022-01-11 19:59:21 +01:00
Greg Chadwick
756610800b [doc] Fix config and expand max-width of docs 2022-01-11 12:49:04 +00:00
Greg Chadwick
596b4d7e92 [doc] Add new Ibex testplan 2022-01-11 12:49:04 +00:00
Pirmin Vogel
8c01488624 [rtl] Document lockstep reset generation mechanism 
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
 2022-01-07 21:25:06 +01:00
Greg Chadwick
a5c55f132e [dv] Add initial coverage plan 2022-01-06 13:47:04 +00:00
Pirmin Vogel
410ffd349d [bitmanip, doc] Update info on bitmanip support and area numbers 
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
 2021-12-16 14:18:00 +01:00
Pirmin Vogel
119ac89130 [syn] Add missing package dependency 
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
 2021-12-16 14:18:00 +01:00
Pirmin Vogel
36c9f4e569 [rtl] Remove redundant comments in decoder 
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
 2021-12-16 14:18:00 +01:00
Pirmin Vogel
92a95cac32 [bitmanip] Add new configuration option for OpenTitan Earl Grey 
RV32BOTEarlGrey selects the Zba, Zbb, Zbc, Zbs sub-extensions from
v.1.0.0 of the bitmanip spec and the Zbf, Zbp, Zbr, Zbt sub-extensions
from draft v.0.93. Zbe (bcompress/bdecompress) is supported by RV32BFull
only.

Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
 2021-12-16 14:18:00 +01:00
Pirmin Vogel
a33a91b232 [lint] Fix some AscentLint errors 
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
 2021-12-13 17:52:20 +00:00
Greg Chadwick
fd1195a148 [dv] Set UVM_VERBOSITY to UVM_LOW 
Vendored in VIP from OpenTitan is very noisy at default UVM_MEDIUM
level, producing multi-GB log files in some instances.
 2021-12-10 15:28:43 +00:00
Greg Chadwick
f1cd3bffc6 [dv] Fix bad reference to instr_req_out 
instr_req_out no longer exists now PMP is handled on the IF/ID
interface.
 2021-12-10 10:40:22 +00:00
Tom Roberts
72a892d62c [rtl] Move PMP checking to IF stage output 
- Instruction addresses are now checked in the IF stage, after the cache
  and after the prefetch buffer.
- To deal with unaligned instructions, the PMP logic checks the current
  address and the next in parallel.
- The spec_branch timing hack has been removed as it's no longer
  relevant with the PMP logic moved.
- Various updates made to the icache testbench to account for the
  changes.
- Relates to #1471

Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
 2021-12-09 18:06:53 +00:00
Pirmin Vogel
fccdd63992 [rtl] Replace always_ff with always @(posedge .. in FPGA regfile 
This resolves lowRISC/Ibex#1485.

Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
 2021-12-09 16:35:31 +01:00
Greg Chadwick
fa3df3b8ee [dv] Fix PMP error handling for icache 
The icache uses a single bit to signify an error. This could either be a
PMP error or a fetch error. Add extra probing so the testbench can
differentiate between the two cases.
 2021-12-09 14:08:05 +00:00
Greg Chadwick
5e7c2cf00a [dv] Add missing copyright header 2021-12-09 14:08:05 +00:00
Greg Chadwick
cedabf062a [dv] Add recoverable NMI handling to cosim 
Ibex implements a custom recoverable NMI handling scheme. This adds
modeling of it to the cosim.
 2021-12-09 14:08:05 +00:00
Greg Chadwick
587dc364e9 [dv] Fix dside memory checking 
Spike may access up to 8 bytes from the current PC, we must assume any
of those accesses are from the iside and skip dside memory checking for
them.
 2021-12-09 14:08:05 +00:00
Greg Chadwick
545a034957 [dv] Fix cosim memory size 
To match with the memory available in the testbench the cosim must
provide 2 GiB of memory.
 2021-12-09 14:08:05 +00:00
Michael Schaffner
045b5707c1 Update google_riscv-dv to google/riscv-dv@6053014 
Update code from upstream repository https://github.com/google/riscv-
dv to revision 605301400555c235564f9336cc5fc220af7e951c

* [style] Break long lines in newly added files (Michael Schaffner)

Signed-off-by: Michael Schaffner <msf@google.com>
 2021-12-08 12:32:48 -08:00
Michael Schaffner
5350c13ae3 [ibex_top] Use correct ECC codeword for '0 reset in regfile 
Signed-off-by: Michael Schaffner <msf@google.com>
 2021-12-08 08:54:54 +00:00
Michael Schaffner
804c538db2 Update lowrisc_ip to lowRISC/opentitan@be1359d27 
Update code from upstream repository
https://github.com/lowRISC/opentitan to revision
be1359d27d0e826e28e6611f318c286253cd05f1

* [secded_gen] Enhance inverted ECC code (Michael Schaffner)
* [rtl] Add CRC32 primitive (Greg Chadwick)
* [syn/cdc] Minor flow fixes in CDC and syn scripts (Michael
  Schaffner)
* [dv] Minor update on mem_model (Weicai Yang)
* [dv/prim_alert] Clean up alert test (Cindy Chen)
* [bazel] Build verilator with bazel (Chris Frantz)
* [cdc] Add support for initial CDC flow with open-source views
  (Michael Schaffner)
* [lc_ctrl/dv,dv_lib,dv_utils,csr_utils] Added JTAG CSR Infrastructure
  (Nigel Scales)
* [prim] Add a lint waiver for dv-only code / ifdefs (Timothy Chen)

Signed-off-by: Michael Schaffner <msf@google.com>
 2021-12-08 08:54:54 +00:00
Pirmin Vogel
c78acac8cc [rtl, bitmanip] Add xperm.[nbh] instruction (Zbp, draft v.0.93) 
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
 2021-12-06 11:14:49 +01:00
Pirmin Vogel
40dab87448 [rtl, bitmanip] Clarify situation around zext.[bh] pseudo-instructions 
This is related to lowRISC/Ibex#1228.

Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
 2021-12-03 22:43:05 +01:00
Pirmin Vogel
da85ce5ecf [rtl] Fix typo in comment 
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
 2021-12-03 22:43:05 +01:00
Pirmin Vogel
16d6f5ea2b [rtl, bitmanip] Align Zbb implementation with draft v.0.93 and v.1.0.0 
This invovles the following changes:
- Rename pcnt to cpop
- Switch encoding of max and minu
- Remove rev from Balanced version, only available in Full version via
  grev (Zbp)
- Include sext.b/h (previously in Zb_tmp)
- Remove slo[i] and sro[i] from Balanced version, only available in Full
  version (Zbp)

Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
 2021-12-03 22:43:05 +01:00
Pirmin Vogel
e765b4dfec [rtl, bitmanip] Align Zbs implementation with draft v.0.93 and v.1.0.0 
This only involves dropping the `s` from the instruction names, i.e.,
sbext becomes bext etc.

Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
 2021-12-03 22:43:05 +01:00
Pirmin Vogel
71b43a83e2 [rtl, bitmanip] Rename bext/bdep to bcompress/bdecompress 
This change is related to the bitmanip draft version 0.94. It's needed
as in draft version 0.93 as well as in version 1.00 sbext from Zbs
changes to bext, leading to two completely different instructions having
the same name.

Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
 2021-12-03 22:43:05 +01:00
Pirmin Vogel
d8e50dcc2c Update google_riscv-dv to google/riscv-dv@ea8dd25 
Update code from upstream repository https://github.com/google/riscv-
dv to revision ea8dd25140178eed13c3e0f3d3a97a0c07ab44a0

* Upgrade bitmanip v.0.92 to v.0.93, enable simultaneous use with
  v.1.00 (Pirmin Vogel)
* Added v1.0.0 bitmanip support (Henrik Fegran)
* Remove the pyucis-viewer from requirements.txt (aneels3)
* Update README.md for PyFlow & add pyucis-viewer in requiremen.txt
  (aneels3)
* Fix typo with fs3_sign (aneels3)
* Add hint_cg and illegal_compressed_instr_cg covergroups (aneels3)
* override deepcopy method (aneels3)
* Fix issue with illegal_instr_testi and randselect (aneels3)
* Fixed b_extension_c() issue (shrujal20)
* Fixed get_rand_spf_dpf_value() issue (shrujal20)
* Add support for RV32C coverage (aneels3)
* Add README.md for PyFlow (aneels3)
* Add gen_timeout for PyFlow (aneels3)
* Issue google/riscv-dv#778 fix, change mie behavior in
  setup_mmode_reg (Henrik Fegran)
* Fixed wrong length of I, S, B-type immediates causing wrong sign
  extension for certain instructions (Henrik Fegran)
* Update riscv_compressed_instr.sv (AryamanAg)
* Update var binary of function convert2bin (AryamanAg)
* Improve status reporting (Philipp Wagner)
* update ml/testlist.yaml to get better coverage (Udi Jonnalagadda)
* add m extension covgroup (ishita71)
* Update pygen_src files (aneels3)

Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
 2021-12-03 22:28:50 +01:00
Michael Schaffner
169785d071 [secded] Switch to inverted ECC codes 
Signed-off-by: Michael Schaffner <msf@google.com>
 2021-12-02 15:14:11 -08:00
Michael Schaffner
4df2221dee Update lowrisc_ip to lowRISC/opentitan@34ba5e45f 
Update code from upstream repository
https://github.com/lowRISC/opentitan to revision
34ba5e45f9af7d8ca6c9bdae8bd11eeeeb669d6c

* [dv] Add new ECC code options to mem_bkdr_util (Michael Schaffner)
* [secded_gen] Define and generate inverted ECC enc/dec modules
  (Michael Schaffner)
* [dv] Only run registers through one csr_rw sequence at once (Rupert
  Swarbrick)
* [alert_handler] Minor lint fix (Michael Schaffner)
* [prim_clock_div] Fix minor Verilator lint warning (Michael
  Schaffner)
* [dvsim/lint] Make message reporting more flexible (Michael
  Schaffner)
* [lint] Unify lint parser scripts (Michael Schaffner)
* [rom_cntrl, dv] Test to verify successful rom check (Prajwala
  Puttappa)
* [dv, dv_macros] Enhance `DV_GET_ENUM_PLUSARG` macro (Srikrishna
  Iyer)
* [sram/dv] Fix mem data check (Weicai Yang)
* [prim] Add flop wrapper for sparse fsm (Timothy Chen)
* [flash_ctrl] Make data / metadata memories a single entry (Timothy
  Chen)
* [dv] Teach encrypt/decrypt_sram_data to support OTBN (Rupert
  Swarbrick)

Signed-off-by: Michael Schaffner <msf@google.com>
 2021-12-02 15:14:11 -08:00
Canberk Topal
53b1732b19 Update lowrisc_ip to lowRISC/opentitan@3a672eb36 
This commit also adds memory manipulation package in ibex repository.

Update code from upstream repository
https://github.com/lowRISC/opentitan to revision
3a672eb36aee5942d0912a15d15055b1d21c33d6

* [mubi] Fix path in auto-gen header (Rupert Swarbrick)
* [dv] Allow using memutil_dpi_scrambled even without prim_ram_1p_scr
  (Rupert Swarbrick)
* [prim] Fix prim_ram_1p_scr Dependencies (Canberk Topal)
* [dv/clk_rst_if] Split clk_rst_if jitter to 2 different values (Eitan
  Shapira)
* [dv] Add external hjson path support in ralgen (Srikrishna Iyer)
* [dv] Add sub RAL block creation knobs (Srikrishna Iyer)
* [pwrmgr] Make rom_ctrl check signals multi-bit (Timothy Chen)
* [dv/alert_handler] Randomize mubi input (Cindy Chen)
* [flash_ctrl] Fix bank erase / info partition issue (Timothy Chen)
* [ci] Fix CI failure (Weicai Yang)
* [Cleanup] Remove lc_tx_e type and replace it with lc_tx_t (Weicai
  Yang)
* [aes] Add gtech synthesis setup (Michael Schaffner)
* [mubi] Enhance mubi_sync with stability check (Timothy Chen)
* [prim] Fix prim_packer_fifo when ClearOnRead is false (Rupert
  Swarbrick)
* [cleanup] Remove mubi4_e and replace it with mubi4_t (Weicai Yang)
* [dv] Fix shape calculations for replicated ECC (Rupert Swarbrick)
* [dv/alert] Support LPG in alert_sender/receiver pair (Cindy Chen)
* [dv] Add a ReadWithIntegrity method to Ecc32MemArea (Rupert
  Swarbrick)
* [dv] Simplify Ecc32MemArea read/write functions (Rupert Swarbrick)
* [prim] Add option to not clear the packer FIFO upon read (Pirmin
  Vogel)
* [dv] Change intg_err test from V3 to V2S (Weicai Yang)
* [util] Delete generate_prim_mubi.py (Rupert Swarbrick)
* [dv] Slightly generalise run_stress_all_with_rand_reset_vseq (Rupert
  Swarbrick)
* [fpv] Fix some assumptions in prim_count (Cindy Chen)
* [prim] quick path to prim_count assertion (Timothy Chen)
* [dv] Support Multiple EDN Interfaces in OpenTitan (Canberk Topal)
* [prim] Add xoshiro256pp primitive. (Vladimir Rozic)
* [dv/prim_alert] Fix async fatal alert regression error (Cindy Chen)
* [prim] Add missing include to prim_xilinx_pad_wrapper (Rupert
  Swarbrick)
* [prim] Add missing include to prim_mubi_dec* (Rupert Swarbrick)
* [dv/prim_alert_receiver] Fix assertion that consumes large mem
  (Cindy Chen)
* [prim] Remove extra semicolon (Weicai Yang)
* [chip,dv] Refactor CSR exclusion method (Srikrishna Iyer)
* [top, all] update connects for mubi (Timothy Chen)
* [flash_ctrl] Add plain text integrity in flash (Timothy Chen)
* [prim] Add time-out functionality to prim_clock_meas (Timothy Chen)
* [prim] Fix DC sythesis error (Weicai Yang)
* [fpv] Fix regression failures (Cindy Chen)
* [dv/ralgen] Update `dv_base_names` input from a string to a list
  (Cindy Chen)
* [dv/ralgen] Update the `dv-base-prefix` optional input (Cindy Chen)
* [doc] Add D2S and V2S checklist items to all checklists (Michael
  Schaffner)
* [dv] Test security countermeasures (Weicai Yang)
* [dv] Fix ASSERT_INIT race condition (Weicai Yang)
* [syn/aes/otbn] Minor fixes to fix block level synthesis (Michael
  Schaffner)
* [all] updated assert rtl ifdef (Timothy Chen)
* [dv] Update TL intg testplan (Weicai Yang)
* [prim] Add prim_fifo_async_sram_adapter to FPV list (Eunchan Kim)
* [spi_device] Upload Cmd/Addr FIFO status revision (Eunchan Kim)
* [dvsim] Modify resolve_branch to handle branch names with forward
  slash. (Todd Broch)
* [prim_clock_inv] Add option to disable FPGA BUFG (Michael Schaffner)
* [ralgen] Be more explicit which tool is called (Philipp Wagner)
* [prim] Tweak prim_sync_reqack_data assertion so it can be disabled
  (Rupert Swarbrick)
* [verible] Rename rule file (Philipp Wagner)
* [dv/base_monitor] Cleaned up base monitor (Rasmus Madsen)
* [fpv] prim_counter_fpv (Cindy Chen)
* [dv/shadow_reg] Cross shadow reg error sequence with csr rw (Cindy
  Chen)
* [dv] Fix scb multi-ral (Weicai Yang)
* [dvsim] Enabling glob-style patterns for -i switch (Srikrishna Iyer)
* [dv] Split sec_cm_testplan into multiple testplans (Weicai Yang)
* [dv/dsim] Remove dsim's system_lib from library path (Guillermo
  Maturana)
* [prim_packer] Resolve width mismatch (Philipp Wagner)
* [prim] Fix lint error in prim_util_memload (Philipp Wagner)
* [prim] Minor fix to make conn checks easy (Srikrishna Iyer)
* [fpv] prim_secded FPV testbench updates bind file naming (Cindy
  Chen)
* [dv_macros.svh] minor cleanup (Srikrishna Iyer)
* [dv,xcelium] minor cleanup (Srikrishna Iyer)
* [dv/shadowed_reset] Add a shadowed_rst_n interface (Cindy Chen)
* [fpv] Update FPV file naming (Cindy Chen)
* [top] Convert to mubi usage in some areas (Timothy Chen)
* [entropy_src] mubi updates (Timothy Chen)
* [prim] Add test for mubi invalid (Timothy Chen)
* [prim_double_lfsr] Add duplicated LFSR primitive (Michael Schaffner)
* [dv] Fix shadow reg backdoor path and enable csr_reset sequence
  (Weicai Yang)
* [prim] Fix unused net (Timothy Chen)
* [dv, clk_rst_if] Improve jitter and add scaling (Srikrishna Iyer)
* [prim] Anchor buffers around register flip flops (Timothy Chen)
* [alert_handler/top] Lint fixes and lc_tx_t to mubi4_t conversions
  (Michael Schaffner)
* [prim_mubi] Replace true/false_value() functions with parameter
  (Michael Schaffner)
* [dv/dsim] Get dsim to work at full chip (Guillermo Maturana)
* [prim] Fixes for prim_count (Timothy Chen)
* [top] Add various anchor points to modules (Timothy Chen)
* [dv/pwrmgr] Add wakeup test sequence (Guillermo Maturana)
* [reggen] Add mubi support into hjson (Timothy Chen)
* [dv/shadow_reg] Fix aes shadow reg failure (Cindy Chen)
* [dv/cdc] CDC simulation model (Udi Jonnalagadda)
* [prim_lfsr/lint] Add temporary waiver for LOOP_VAR_OP lint error
  (Michael Schaffner)
* [prim_clock_buf] Add lint waiver for unused parameter (Michael
  Schaffner)
* [dvsim] Correctly set self_dir for included Hjson files (Philipp
  Wagner)
* [util] Add tooling support for V2S milestone (Srikrishna Iyer)
* [prim_mubi] Add decoder module similar to prim_lc_dec (Michael
  Schaffner)
* [prim_mubi] Add mubi sender and sync primitives (Michael Schaffner)
* [prim_mubi_pkg] Switch to True/False terminology (Michael Schaffner)
* [prim] Minor work-around for xcelium (Timothy Chen)

Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
 2021-11-29 17:25:30 +00:00
Tom Roberts
1bbe27effe [dv/icache] Add missing window reset call 
The cache hit-rate tracking logic needs to be reset on every
invalidation.

Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
 2021-11-18 15:54:29 +00:00
Sam Shahrestani
ab4041c439 Move NT branch addr calculation to ID stage 2021-11-18 13:05:19 +00:00
Rupert Swarbrick
b66f199151 Update lowrisc_ip to lowRISC/opentitan@ad629e3e6 
Update code from upstream repository
https://github.com/lowRISC/opentitan to revision
ad629e3e6e70c5eaa3c2dd68457b0a020448b35f

* [dvsim] Introduce {self_dir} as variable (Philipp Wagner)
* [dvsim] Small cleanups (Philipp Wagner)
* [prim_lfsr] Minor lint fix (Michael Schaffner)
* [dv] Update sec_cm testplan (Weicai Yang)
* [prim/lint] Move waiver to correct waiver file (Michael Schaffner)
* [prim_assert] Relocate waivers to dedicated prim_assert.waiver file
  (Michael Schaffner)
* [alert_handler] Lint fixes and waiver updates (Michael Schaffner)
* [prim_lc_receiver] Add parameter to select reset value (Michael
  Schaffner)
* [lint] Add lint waiver for IP regfiles with shadow resets (Michael
  Schaffner)
* [fpv] Fix Verible lint errors (Philipp Wagner)
* [prim_lfsr] Minor lint fixes (Timothy Chen)
* [clkmgr] Fix measurement control CDC (Timothy Chen)
* [fpv/prim_counter] Pad one bit to include overflow case (Cindy Chen)
* [fpv] Fix issue lowRISC#8371 (Zeeshan Rafique)
* [flash_ctrl] Flash ctrl security hardening (Timothy Chen)
* [dv] Fix CI error (Cindy Chen)
* [prim_alert_*] Extend SVAs for FPV (Michael Schaffner)
* [prim_alert_*] Update DV TB to respect initialization timing
  (Michael Schaffner)
* [prim_alert_rxtx_fpv] Update FPV environment and fix SVAs (Michael
  Schaffner)
* [prim_alert_sender] Update sender to support in-band reset mechanism
  (Michael Schaffner)
* [prim_alert_sender] Simplify sender and clear ping req upon sigint
  (Michael Schaffner)
* [prim_lc_sender] Add option to select reset value (Michael
  Schaffner)
* [prim] Correct assertion valid term (Timothy Chen)
* [prim_lc_combine] Align behavior of lc combine with mubi functions
  (Michael Schaffner)
* [fpv/tool] Support GUI mode on dvsim (Cindy Chen)
* [prim_lfsr] Further permutation refinements for SBox layer (Michael
  Schaffner)
* [dv/shadow_reg] Shadow register write by field (Cindy Chen)
* [prim] Fix the edge type (Eunchan Kim)
* [checklist] Updates to checklist for D2 status (Tom Roberts)
* [prim_mubi_pkg] Add a generic multibit type and associated functions
  (Michael Schaffner)
* [prim] Minor fix and clarification to prim_count (Timothy Chen)
* [keymgr/dv] Update testplan and covergroup plan (Weicai Yang)
* [prim_lc_combine] Fix parameterization error (Michael Schaffner)
* [fpv/prim_count] Small update on prim_count assertions (Cindy Chen)
* [dv] Add ip_name in reg_block (Weicai Yang)
* [keymgr] Finalize keymgr hardening (Timothy Chen)
* [prim_lc_combine] Add a prim to compute logical AND/OR for LC
  signals (Michael Schaffner)
* [dv] Remove common_cov_excl.el from unr.cfg (Weicai Yang)
* [dv/top_level] Loop through the SW test multiple times (Cindy Chen)
* [flash_ctrl] Various clean-up and updates (Timothy Chen)
* [prim] Change prim_reg_cdc assertions (Timothy Chen)
* [prim, keymgr] Migrate keymgr_cnt to prim_count (Timothy Chen)
* [sw dv] Multi-site support for Verilator (Martin Lueker-Boden)
* [dv/csr] Update write exclusion wdata value (Cindy Chen)
* [dv/dv_base_reg] remove debug display (Cindy Chen)
* [dv/shadow_reg] Fix alert shadow_reg regression error (Cindy Chen)
* [top] Integrate ast into fpga (Timothy Chen)
* [prim_lfsr] Improve statistics of non-linear output (Michael
  Schaffner)
* [prim_esc_receiver] Fix response toggling corner case (Michael
  Schaffner)
* option to use partner ast_pkg (Sharon Topaz)
* [dv/prim_esc] Double the ping timeout cycles (Cindy Chen)
* [dv] Use sed to add -elfile for each excl file (Weicai Yang)
* [dv] Fix coverage report error (Weicai Yang)
* [dv] Update common exclusion file (Weicai Yang)
* [dv/prim_esc] Improve FSM coverage (Cindy Chen)
* [reggen] Add a check to limit the swaccess type for shadow regs
  (Michael Schaffner)
* [prim_subreg_shadow] Fix for W1S/W0C corner case (Michael Schaffner)
* [prim_subreg_shadow] Disallow phase updates when storage err is
  present (Michael Schaffner)
* [dvsim] Add passing count by milestone in reports (Srikrishna Iyer)
* [dv/tool] Include toggle coverage for prim_alert_sender in
  cover_reg_top (Cindy Chen)
* [clkmgr] Harden clock manager through frequency measurements
  (Timothy Chen)
* [dv] Only enable VCS -kdb when dumping waves (Weicai Yang)
* [dv] Fix shadow reg (Weicai Yang)
* [dvsim] Allow non-integral values of --reseed-multiplier (Rupert
  Swarbrick)
* [ast] Fixes for various ast issues (Timothy Chen)
* [prim_esc_receiver] Assert escalation in case of sigint error
  (Michael Schaffner)
* [prim_esc_receiver] Minor signal renaming for consistency (Michael
  Schaffner)
* [dv/alert_handler] Support shadow register sequence (Cindy Chen)
* [verilator] Use FileSz rather than MemSz when flattening ELF files
  (Michael Munday)
* [prim_subreg_shadow] Only assert QE when committed_reg is written
  (Michael Schaffner)
* [dv,verilator] Round up SV_MEM_WIDTH_BYTES to a multiple of 4
  (Rupert Swarbrick)
* [prim] Add missing include (Pirmin Vogel)
* [dv/cover_cfg] Exclude prim_alert/esc from xcelium (Cindy Chen)
* [dv/cover_cfg] Exclude prim_alert/esc pairs (Cindy Chen)
* [clkmgr] Use local BUFHCE clock gates on FPGA (Pirmin Vogel)
* [prim_prince] Mark "leaf" functions in prince_ref.h as static inline
  (Rupert Swarbrick)
* [dv/shadow_reg] Check status after shadow_reg write (Cindy Chen)
* [dv/shadwo_reg] Shadow reg common sequence update (Cindy Chen)
* [otp_ctrl/lc_ctrl] Add 32bit OTP vendor test ctrl/status regs to LC
  TAP (Michael Schaffner)
* [otp_ctrl] Add VENDOR_TEST partition (Michael Schaffner)
* [prim] Edge Detector (Eunchan Kim)
* [prim_diff_decode] Fix asynchronous assertions (Michael Schaffner)
* [spi_device] Instantiate Upload module (Eunchan Kim)
* [dv] Add sv_flist_gen_flags HJson var for FuseSoc (Srikrishna Iyer)
* [dv, xcelium] Properly pass excl files to IMC (Srikrishna Iyer)
* [reg] Fix shadow reg update during storage error (Timothy Chen)
* [regfile] Refactor cdc handling to the reg level (Timothy Chen)
* [dv/prim_esc] Add a testplan and increase coverage (Cindy Chen)
* [dv] Update TLUL and EDN frequency (Weicai Yang)
* [rstmgr, top] Add support for shadow resets (Timothy Chen)
* [dv] Update Xcelium cover ccf (Srikrishna Iyer)
* [dv] reduce seeds for CSR tests (Weicai Yang)
* [usb/top] Remove AND gates on non-AON domain and rename 3.3V signal
  (Michael Schaffner)
* [dv/prim_alert] Improvement on prim_alert tb (Cindy Chen)
* [prim] FIFO SRAM Adapter fix (Eunchan Kim)
* [prim] Add Write Mask port (Eunchan Kim)
* [dv] Fix timescale issue with Xcelium (Weicai Yang)
* [dv/prim_esc] Fix prim_esc regression error (Cindy Chen)
* [dv/dv_base_reg] change from uvm_low to uvm_high (Cindy Chen)
* [sram_ctrl] Harden initialization counter (Michael Schaffner)
* [tools/uvmdvgen] Fix path in testplan inclusion (Guillermo Maturana)
* [dv] Change stress_all_with_rand_reset to V3 (Weicai Yang)
* [dv] fix tl error coverage (Weicai Yang)
* [dv] Add macro DV_GET_ENUM_PLUSARG (Weicai Yang)
* [prim] SRAM Async FIFO (Eunchan Kim)
* [dv, xcelium] Fix statement coverage extraction (Srikrishna Iyer)
* [dvsim] Minor fixes to coverage extraction (Srikrishna Iyer)
* [prim_lfsr] Do not shadow |state| variable (Philipp Wagner)
* [prim] Add non-linear out option to prim_lfsr (Timothy Chen)
* [dv] Constrain TLUL to 24Mhz or higher (Weicai Yang)
* [primgen] Instantiate tech libs in stable order (Philipp Wagner)
* [primgen] Actually find the Verible Python wrapper (Philipp Wagner)
* [dv/prim_esc] fix regression error (Cindy Chen)
* [dv] Fix shadow reg predict (Weicai Yang)
* [dv/common] Exclude assertion coverage from IP level testbench
  (Cindy Chen)
* [dv/prince] hit additional toggle coverpoints (Udi Jonnalagadda)
* [sram_ctrl] Update docs (Michael Schaffner)
* [sram_ctrl] Absorb prim_ram_1p_scr (Michael Schaffner)
* [dv/prim_alert/esc] Improvements for prim_alert/esc_tb (Cindy Chen)
* [dv/dvsim] Add "testfile" grading option (Guillermo Maturana)
* [dv/prim_esc] Direct test for prim_rx/tx (Cindy Chen)
* [dv/utils] added 6MHz to clk_freq_mhz_e (Dror Kabely)
* [prim_xor2/lint] Add waiver for .* use in generated prim (Michael
  Schaffner)
* [dv, doc] Replace all 'dv.plan' with testplan (Srikrishna Iyer)
* Fix the testplan link in dvsim code (Srikrishna Iyer)
* [dv/dsim] Add dsim workaround for issue 242 (Guillermo Maturana)
* [util, reggen] Support standardized cdc handling for regfile
  (Timothy Chen)
* [dv/shadow_reg] Align shadow_reg field update behavior (Cindy Chen)
* [dvsim] Fix publish report summary typo (Cindy Chen)
* [rtl/prim_alert_sender] Allow ping_req to stay high without error
  (Cindy Chen)
* [dvsim] Separate publish report from dvsim flow [PART3] (Cindy Chen)
* [dv/prim_alert] Add a testbench for prim_alert (Cindy Chen)
* [otp_ctrl] Connect test-related GPIO signal (Michael Schaffner)
* [prim_subreg_shadow] Make local parameter a localparam (Philipp
  Wagner)
* [prim_subreg] Make software access type an enum (Philipp Wagner)
* [rtl/prim_diff_decode] Add prim_flop_2sync dependency (Cindy Chen)
* [otp_ctrl] Update AscentLint waiver file (Michael Schaffner)
* [edn] Add MaxLatency assertion (Eunchan Kim)
* [prim_subreg_shadow] Correct write data signal usage (Michael
  Schaffner)
* [script/dvsim] Separate publish report from dvsim flow [PART2]
  (Cindy Chen)
* [prim_lfsr] Fix assertion issue occuring right after reset (Michael
  Schaffner)
* [dv/shadow_reg] Handle CSR automated sequence write abort (Cindy
  Chen)
* [dv/dv_lib] Add post_apply_reset for extra delay (Guillermo
  Maturana)
* [dv] Add function coverage plan for tl_errors, tl_intg_err (Weicai
  Yang)
* [dv] Remove tl_intg_err in top-level and increase seeds for
  tl_intg_err (Weicai Yang)
* [dv/shadow_reg] Fix alert shadow reg regression error (Cindy Chen)

Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
 2021-11-16 10:49:23 +00:00
Greg Chadwick
e70add7228 [ci] Add co-simulation testing of CoreMark 2021-11-12 09:39:38 +00:00
Greg Chadwick
63ac629d10 [coremark] Add option to coremark build to suppress pcount dump 
When using cosim checking performance counters won't match between ISS
and RTL. This option allows coremark to be run under cosim checking.
 2021-11-12 09:39:38 +00:00
Greg Chadwick
c3dd66e9fa [cosim] Update documentation for cosim 
Also adjusts quick install instructions to use /opt/spike-cosim as
that's the path used by the pre-packaged version.
 2021-11-12 09:39:38 +00:00
Greg Chadwick
84d2d6ad3f [cosim] Add Simple System with cosim 2021-11-12 09:39:38 +00:00
Greg Chadwick
580ddaad13 [simple_system] Refactor Simple System 
Refactor Simple System into a C++ class. This enables easy extension of
Simple System.
 2021-11-12 09:39:38 +00:00
Greg Chadwick
b57cad5387 [dv] Add matched instruction count to cosim 2021-11-12 09:39:38 +00:00
Greg Chadwick
c10b56ed17 [dv] Adjust cosim include paths 
Some Spike include files can clash with libelf include files. Avoid
directly adding riscv and fesvr directories to include path to prevent
this.
 2021-11-12 09:39:38 +00:00
Michael Munday
c35472abb9 [bitmanip][zba] Add support for Zba (address calculation) extension 
Add support for the Zba extension added in v0.93 of the bit manipulation
specification (unchanged in v1.0.0). The new instructions added are:

  - sh1add: rd = (rs1 << 1) + rs2
  - sh2add: rd = (rs1 << 2) + rs2
  - sh3add: rd = (rs1 << 3) + rs2

The instructions are single cycle and have been implemented using the
adder in the ALU.

Signed-off-by: Michael Munday <mike.munday@lowrisc.org>
 2021-11-01 09:58:01 +00:00