This adds some new `rvfi_ext` signals that are needed by the
co-simulation environment.
It also fixes/alters `rvfi_trap`. Previously it wouldn't work correctly
in various cases. Now it is fully functional, though it's meaning
includes more trap cases than the RVFI spec strictly includes. It is now
set for any instruction that produces a synchronous trap (everything bar
interrupts).
This matches the priority used in Spike.
This also fixes an issue in the DV where the priority of
external/software/timer interrupts wasn't calculated correctly.
Newer versions of sv2v carry through elaboration system tasks like
$fatal. ibex_top_tracing uses $fatal, but isn't actually used in the
syn_yosys flow. By using -defer, unused modules like ibex_top_tracing
are not elaborated in Yosys.
When the writeback stage is present the retired instruction counter
(minstret) and the retired compressed instruction counter could see an
off by one error when an instruction was in the writeback stage when
reading the counters. With this fix the ID stage observes the
incremented value of the counters when an instruction that would
increment them is in writeback.
Without this an instruction taking an exception will enter WB whilst
simultaneously remaining in ID. This didn't cause any known functional
issues as in the scenarios it occurred the RF write was disabled and the
WB stage eventually gets flushed. However it's still bad behaviour and
could lead to functional issues when RTL changes. It also eases the
co-simulation DV implementation.
Previously the monitor would emit write transactions the cycle the
request is seen and emit read transactions the cycle the response is
seen. This allowed later write transactions to be emitted before earlier
reads (where a new write transaction is started the cycle a read
response returns).
Now both read and write transactions are emitted when their response is
seen.
In addition the error field from the response is copied into the
transaction.
Extra bits are added alongside read/write data for the instruction and
data buses to facilitate data integrity checking.
Ibex testbench extended to generate the expected bits.
All other top-levels modified to add the new signals (which are mostly
ignored).
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
Previously the raw incremented address was used which is the calculated
address + 4. This is confusing as it refers to a byte that wouldn't be
accessed (e.g. a lw at 0x8000009e which faults on the access to
0x8000000a0, would report an mtval of 0x8000000a2). With this change
mtval will refer to the first byte on the other half of the word
boundary the unaligned access crosses.
Random constants are sent through the hierarchy as parameters in-line
with other OpenTitan modules.
Further detail on this mechanism can be found in lowrisc/opentitan#2229
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
mseccfg and mseccfgh have changed their addresses. This updates to the
newly allocated values.
The ePMP specification is now available as a versioned PDF,
documentation is updated to point to that removing the local PDF copy.
This commit adds power analysis scripts to the Arty A7
example design. They can be used by setting the newly
added `FPGAPowerAnalysis` parameter to 1.
Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
1-Port RAM is removed because of both execution and performance
issues. CLKIN1_PERIOD parameter is defined in clkgen module
for Vivado simulations.
Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
This commit updates link.ld RAM length to include max BRAM capacity
for Arty A7-35. It also changes coremark makefile to include a .vmem
output, which then can be used for FPGA implementations.
Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
A minor change to use the Width parameter of prim_buf. No functional
impact but stops the hierarchy from being cluttered with hundreds of
generate contexts in the top level.
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
This parameter forces a reset of all registers inside the core. This is
required to guarantee a common starting point for lockstep and thus
prevent spurious lockstep failure alerts.
Another minor change in this commit rearranges the writeback stage
multiplexing to gate incoming lsu write data when not valid. This stops
any X values from the data bus propagating to the register file
signalling (and thus to the lockstep comparison) which would cause the
lockstep alert to be X. It has the side effect of possibly reducing
power consumption in the register file.
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
This invocation would break:
make -C examples/sw/led/ CC=/opt/lowrisc-toolchain-gcc-rv32imc-20210412-1/bin/riscv32-unknown-elf-gcc
because the "-gcc" occurence inside the directory name would also be replaced.
Fix by first deriving CROSS_COMPILE from CC, then conditionally build other tool file names/paths.
Signed-off-by: Leon Woestenberg <leon@sidebranch.com>
We're already redirecting stdout to sim.log in run_rtl.py. Specifying
'-l' as well meant that VCS opened sim.log in a separate FD.
Suprisingly enough, this mostly worked, but not always! Just write
once :-)
This commits adds a yaml based intermediate format for test results.
compare.py serialises a TestRunResult (a named tuple type) into this
format for each test run it checks. collect_results.py reads them all
back in to produce reports.
Three reports are output:
- regr.log - plain text report much like the one previously produced
- regr_junit.xml, regr_junit_merged.xml - JUnit report format, the
_merged version batches together multiple tests to appear to be a
single test case under a test suite. This gives better results with
Azure's JUnit reporting.
This signal used to be a one shot enable out of reset. We need an option
to pause execution for OpenTitan, so fetch_enable is extended to cover
that.
The signal is already driven low by the testbench at the end of test.
This is moved after the performance counter reads to ensure they can
complete.
Fixes#1105
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
Fix the reset polarity in the irq driver (clears irq signals to zero
on reset rather than them being x) plus remove an unused signal.
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
The test loops around waiting for the core to sleep then sending
interrupts to wake it. In some cases, the sequence sends an interrupt
that isn't enabled. It never gets back to try again with a new interrupt
since the test is waiting to see wfi first. This change removes that
requirement since it is redundant anyway (have to see wfi to sleep).
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
