The ic_scr_key_valid field indicates whether the ICache scrambling key
is valid.
CPUCTRL is also renamed CPUCTRLSTS as it contains both control and
status bits.
Extends RVFI connections further to include 30 mhpmcounterX registers.
Sets them up before every cosim step to let Spike know their real values.
Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
Updated the parameters with respect to top_earlgrey.hjson in OpenTitan
repository. For other builds, kept the previously undeclared parameters
as their default values.
Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
This commit includes switching to a scrambling RAM primitive for
ICache data and tag RAMs. Also introduces minor changes to ICache
to handle scrambling key valid signal.
It also includes a minor bug fix regarding not initializing
`fill_way_q` signal without ResetAll parameter. When the parameter
is not set and we have our first hit right after ICache enables,
the signal hangs.
Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
https://github.com/lowRISC/opentitan/pull/2311 added the Verilator
memutils to OpenTitan as upstream. This commit is the second part of the
story, removing the code from the Ibex repository, and vendoring it back
in from OpenTitan.
This also superseded #844, which has now been included through
OpenTitan.
DPI access is suggested and more generic than Verilator direct signal
access. This changes the access to the performance counters from the
Verilator testbench to use DPI instead of directly accessing the
array.
Signed-off-by: Stefan Wallentowitz <stefan.wallentowitz@hm.edu>
The option to limit the verilator simulation's maximum number of cycles was
implemented in terms of the `time_` variable, which counts half cycles. This
patch makes the limit respect the requested number of full cycles.
The patch divides `time_` by 2, instead of multiplying `term_after_cycles_`
by 2, as that better conveys the intended semantics, and slightly increases
the range of the limit. Related computations were modified for consistency.
In `VerilatorMemUtil::WriteElfToMem`, the verilator memory is written
with the ELF segment data, 4 bytes at a time . If the segment size isn't
a multiple of 4 (e.g. when using the RISC-V C extension) the last word
wouldn't be written. This patch rounds the size up to a multiple of 4,
solving that issue.
In case one of the arguments is '-h' the parsing of the arguments is
aborted and only `PrintHelp()` of *verilator_sim_ctrl.cc* is executed.
Do not abort at this point in order to forward the arguments to the
registered extensions. This allows to execute the respective
`PrintHelp()` function and print the help message. For example
`VerilatorMemUtil` needs to parse the arguments in order to print the
help message.
The execution of the simulation is still terminated as `exit_app` is set
and then evaluated after parsing of the registered extensions.
As described in https://github.com/lowRISC/opentitan/issues/1245,
the Ibex Verliator ELF processing does not exactly follow the algorithm
for the "binary" target of objcopy (which it is intended to mimic).
In particular, sections as denoted by program headers are laid down
strictly sequentially, ignoring their specified p_paddr -- and
resulting in a corrupted in-memory image for ELF images that have
unordered program headers.
The VerilatorSimCtrl class was always intended to be used only once in
an application, since it sets up a global signal handler and needs to be
accessible from DPI modules. This accessibility was achieved through a
global variable `simctrl`.
With this commit the VerilatorSimCtrl is switched to a singleton class.
The instance is accessible through `VerilatorSimCtrl::GetInstance()`.
The downside of that approach is that we loose the constructor
arguments, and need to deal with a class which potentially hasn't top or
the clock and reset signals set.
All functions in simutil_verilator return booleans to indicate
success/failure, where 1 == true, and 0 == false.
simutil_verilator_set_mem() returns an int due to DPI interface
restrictions. Before, 0 meant success, and 1 meant error.
To keep things nice and consistent, turn things around and align with
the bool meaning.
Support initialization of memory by loading content from ELF files.
All segments of the ELF file with the type `PT_LOAD` are merged into a
temporary buffer and then forwarded to a predefined memory.
This is an addition for setting the memories with VMEM files.
Memories must implement `simutil_verilator_set_mem` to support the
setting of values with a width of 32 bits. A return value of 0 must
indicate a successful operation and 1 an error.
Memories are defined by a call to `RegisterMemoryArea()` before the
execution of the simulation, at which point the arguments are parsed and
the initialization is started. The memories are identified by unique
name. The design specific location is used to set the SystemVerilog
scope.
Registered memories can be printed by using `-l list`. The unique name
is used for `-l name,file.elf` together with the file path.
An optional part of the argument is the type of the file, `elf` or
`vmem`, and if not provided it is attempted to detect the type by
looking at the file extension.
The memory specific arguments which already existed accept now also ELF
files. They use predefined names and are included to keep the interface
stable.
Contents of an ELF segment which has a bigger memory size than file size
are not set. This is typically required for BSS sections for zero-ing
the memory.
Previously, verilated_toplevel.h contained a macro, VERILATED_TOPLEVEL()
to produce a class TOPLEVEL (whatever the toplevel happens to be). This
required all compilation units referring to that TOPLEVEL class to call
the macro.
After this change, the class is always generated in
verilated_toplevel.h. For that to work, a new define TOPLEVEL_NAME must
be globally set (e.g. passed to the compiler with -DTOPLEVEL_NAME=xxx).
