Previously it had two packed dimensions. In general we prefer the use of
unpacked arrays for this kind of usage. In particular this had an impact
on trace viewing in GTKWave, the two dimensions were flattened into a
single large bus which made determining individual register values
tricky.
core_ibex_directed_test has a 'disable fork' that was killing processes
that were running sequences. Another part of the testbench waits for
those sequences to finish. When this 'disable fork' happens too early
the sequences are killed before they finish so the testbench never
terminated and times out. Instead ensure the sequences have finished
before doing the 'disable fork'.
The ic_scr_key_valid field indicates whether the ICache scrambling key
is valid.
CPUCTRL is also renamed CPUCTRLSTS as it contains both control and
status bits.
Referring to specific parts of a specific version of the specification
can be brittle as all of these references need to be updated when we
shift specification versions. It's also redundant it should be generally
understood Ibex implements the RISC-V specifications and many lines
could have comments that point to the part of the specification they are
implementing. Rather than having a few of these for no particular reason
easier to just remove them all.
This is specification change between the v1.11 and v1.12 privileged
architectures. Previously mprv wasn't altered on mret. Now if returning
to a privilege level other than M mode mprv must be cleared.
This adds the following CSRs to support the v1.12 priviledged spec.
- MSTATUSH
- MCONFIGPTR
- MENVCFG
- MENVCFGH
MCONFIGPTR is read only and has its value provided by a ibex_pkg
parameter CSR_MCONFIGPTR_VALUE which is set to 0. Implementors can alter
this value if needed.
All the other CSRs ignore writes and read as 0.
RISCV-DV by default sets up some PMP regions. This leads to PMP failures
within riscv_mem_error_test which it isn't expecting. Suppress the PMP
setup to prevent this issue.
Spike has a hack that decrements mcycle/minstret when written.
Previously this was not handled correctly by cosim. As we can only write
32 bits at a time two writes must be used and incremented to counteract
the decrementing handled carefully.
The prior system of using a patch to alter the riscv_dv_setting.sv file
has been removed and replaced with a mako templating based approach.
Fixes#1787
- Increase iterations to 20 because double faults are less likely.
- Remove restriction on MPRV randomization.
Signed-off-by: Marno van der Maas <mvdmaas+git@lowrisc.org>
Update code from upstream repository https://github.com/google/riscv-
dv to revision 68e3bcac7293ac79067f0d8196bb973bd7c889cf
* [pmp] Remove restriction on using NAPOT when granularity = 0 (Marno
van der Maas)
* [pmp] Add PMP entries for data in case of MML or MMWP (Marno van der
Maas)
* [pmp] Add already_configured flag to skip address in PMP routine
(Marno van der Maas)
* [pmp] Fix constraint and CSR write test in MML mode (Marno van der
Maas)
* [pmp] Use random address instead of offset for full random test
(Marno van der Maas)
* [pmp] Allow specifying address zero in `+pmp_region_%0d` (Marno van
der Maas)
* [pmp] Randomizing entry for instructions for PMP randomization
(Marno van der Maas)
* [lint] Remove trailing whitespace (Marno van der Maas)
* Tweak CSR constraints for more even read/write distribution (Greg
Chadwick)
* [lint] Replace tabs with spaces (Marno van der Maas)
* [pmp] No PMP exception handler when no PMP support (Greg Chadwick)
* Expand CSR instruction constraint functionality (Greg Chadwick)
* Refactor CSR instruction into their own class (Greg Chadwick)
Signed-off-by: Marno van der Maas <mvdmaas+git@lowrisc.org>
We are running with cosim by default now, and no longer support COSIM=0. Hence
this option and all downstream conditional paths are no longer required.
