Rupert Swarbrick
2f1e188346
Fix port list in top_artya7 example
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The "alert_major" port was split into "internal" and "bus" parts back
in commit 9943f9a
2022-03-15 15:37:03 +00:00
Greg Chadwick
e53b033962
[examples/fpga] Fix memory interface
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Logic driving instr_gnt/data_gnt violated Ibex memory protocol. It just
happened to work until a recent change.
Fixes #1500
2022-01-14 09:00:48 +00:00
Greg Chadwick
2ec8d7433e
[examples/fpga] Use 64 kB memory by default
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The 256 kB is too large for the Arty-A7 with the A7-35T. Only use it
for the FPGA power analysis configuration.
2022-01-14 09:00:48 +00:00
Tom Roberts
48f11c6733
[rtl] Add bus integrity checking
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Extra bits are added alongside read/write data for the instruction and
data buses to facilitate data integrity checking.
Ibex testbench extended to generate the expected bits.
All other top-levels modified to add the new signals (which are mostly
ignored).
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
2021-08-26 16:55:26 +01:00
Canberk Topal
1b1247e1de
[fpga] Changed to 2p_ram for FPGA top level
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1-Port RAM is removed because of both execution and performance
issues. CLKIN1_PERIOD parameter is defined in clkgen module
for Vivado simulations.
Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
2021-08-03 16:51:16 +01:00
Tom Roberts
7ac218f3ae
[rtl] Wire scan_rst_ni through ibex_top_tracing
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Better to have the tracing top consistent with the non-tracing top.
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
2021-04-21 12:41:24 +01:00
Tom Roberts
6a3200929b
[rtl] Add a new top level plus wiring
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This commit creates a new top level wrapping the core, register file and
icache RAMs. The tracing top level is also renamed to ibex_top_tracing
to match. This new top level is intended to enable a dual core lockstep
implementation of Ibex.
There are no functional changes in this commit, only wiring.
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
2021-04-07 12:07:38 +01:00
Tom Roberts
2c75c2b2ec
Update lowrisc_ip to lowRISC/opentitan@1ae03937f
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Update code from upstream repository
https://github.com/lowRISC/opentitan to revision
1ae03937f0bb4b146bb6e736bccb4821bfda556b
* [prim/fifo_async] Add assertions on pointers (Tom Roberts)
* [prim/fifo_async] Add support for Depth <= 2 (Tom Roberts)
* [prim/fifo_async] Code tidy-up (Tom Roberts)
* [top / ast] Continued ast integration (Timothy Chen)
* [dvsim] Use bash when running make underneath (Srikrishna Iyer)
* [prim] Increase maximum width for prim_util_memload to 312 (Greg
Chadwick)
* [sram_ctrl] Fix potential back-to-back partial write bug (Michael
Schaffner)
* [dvsim] Fix for lowRISC/opentitan#5527 (Srikrishna Iyer)
* [lint] Waive Verilator UNUSED warnings for packages (Rupert
Swarbrick)
* [uvmdvgen] Update DV doc path and terminology (Srikrishna Iyer)
* [clkmgr] Fix dft issues (Timothy Chen)
* [util] add `dec` types to prim_secded_pkg (Udi Jonnalagadda)
* [util] minor updates to secded_gen (Udi Jonnalagadda)
* [lint] Fix a bunch of lint warnings related to long lines (>100
chars) (Michael Schaffner)
* [dv] Update common intr_test seq (Weicai Yang)
* [util] Slight refactor of secded_gen.py (Timothy Chen)
* [tlul] Add memory transmission integrity checks (Timothy Chen)
* [dvsim] Move clean_odirs to `util.py` (Srikrishna Iyer)
* [dvsim] Split Deploy into Deploy and Launcher (Srikrishna Iyer)
* [dvsim] Add utils.TS_FORMAT* vars (Srikrishna Iyer)
* [dv/lock_reg] Update IPs to adopt the lock_reg changes (Cindy Chen)
* [dv/enable_regs] Support enable registers have more than one field
(Cindy Chen)
* [dv/base_reg] use m_field instead of accessing field (Cindy Chen)
* [dv/sram] add SRAM scrambling model for DV (Udi Jonnalagadda)
* [dv/tools] Updated Coverage flow for xcelium (Rasmus Madsen)
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
2021-03-12 16:15:22 +00:00
Tom Roberts
ee8d1051bb
[rtl] Add crash dump outputs
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Relates to lowrisc/opentitan#4618
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
2021-03-01 10:12:04 +00:00
Pirmin Vogel
9eebf52590
Fix RegFile parameter overriding in ArtyA7 example
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Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
2020-08-21 14:06:36 +01:00
Pirmin Vogel
9559bbb6ff
Add RegFile parameter for selecting register file implementation
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Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
2020-08-21 14:20:34 +02:00
Tom Roberts
aae437d75b
[rtl] Add alert outputs
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- Add a major and minor alert output which can be used by the system to
react to fault injection attacks
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
2020-07-15 09:50:23 +01:00
Rupert Swarbrick
006617f95a
Fix SRAM initialisation for fpga/artya example
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This now gets passed to the underlying primitive as a
parameter (instead of a define).
2020-07-03 16:06:48 +01:00
Stefan Tauner
0f0571f0ee
FPGA example: add support for the Arty A7-35
2020-01-27 20:18:17 +00:00
