- Instantiate generic PMP module
- Wire up I-side and D-side PMP faults
- The output of the PMP check is used to gate external bus requests from the
I-side and LSU
- Each of those units progresses with their request as-if it was granted
externally and registers the PMP error
- The error is then sent to the controller at the appropriate time to trigger
an exception
This commit adds 15 local fast interrupt lines managed through
the `mie` and `mip` CSRs directly, and removes the old legacy
interrupts including the internal controller.
This file doesn't contain defines any more, but a normal SV package.
The diff is best viewed without whitespace changes, as the reindents
cause a lof of diff noise.
Fixeslowrisc/ibex#173
The ibex_tracer_define.sv file was removed from the FuseSoC core files,
but not from the src_files.yml (for Bender) and the .f file.
This is in line with the changes made in
f12b94c2a2.
- Move ibex_tracer_defines.sv and ibex_defines.sv out of the 'include'
directory, since these files are not actually included.
- Remove ibex_config.sv, it's mostly unused code. The remaining defines,
SYNTHESIS, ASIC_SYNTHESIS, TRACE_EXECUTION, and CHECK_MISALIGNED should
be set through command-line flags to the simulation/synthesis tools.
Initial version by Nils Gräf.
This commit was prepared by the following script, followed by manual
fixes as needed.
```sh
sed -e 's/zeroriscy/ibex/g' -i.bak *.sv *.md *.yml
sed -e 's/zero-riscy/ibex/g' -i.bak *.sv *.md *.yml
sed -e 's/zeroriscy/ibex/g' -i.bak include/*.sv
sed -e 's/zero-riscy/ibex/g' -i.bak include/*.sv
sed -e 's/cluster_clock_gating/clock_gating/g' -i.bak *.sv
rm -f *.bak
rm -f include/*.bak
find . -name 'zeroriscy_*' -exec bash -c 'file={}; git mv $file ${file/zeroriscy/ibex}' \;
```
