It randomly writes to fields of cpuctrlsts to enable and disable data
independent timing, dummy instruction insertion and the icache. This is
used in riscv_debug_basic_test and riscv_single_interrupt_test to see
interrupts and debug requests when dummy instruction insertion and data
independent timing is enabled.
Update code from upstream repository https://github.com/google/riscv-
dv to revision 68ab8230c52ec66b393c04394aef4d6082ee53b4
* [pmp] Ensure MML PMP configurations don't dominate. (Greg Chadwick)
* [pmp] Add option to constrain addresses to stay in 32-bit space
(Greg Chadwick)
* randomizing mstatus.MIE when priv mode is lower than machine (Saad
Khalid)
Signed-off-by: Greg Chadwick <gac@lowrisc.org>
This is used in riscv_pmp_full_random_test as some executions of that
test run very slowly. These are still valuable so the timeout is used to
ensure they don't take too long but still result in a pass.
This helps reduce repetition in the CI yaml in preparation for adding
more directed tests.
This is a very basic script and will be replaced by a more complete
system at a later point.
cov_merge.tcl has been patched so the Ibex regression can pass through
coverage directories via a file. However this breaks dvsim based flows,
in particular the icache coverage merge.
This patch checks to see if the file is provided, if not it uses the
original merge method that's compatible with dvsim.
The new instruction stream randomly chooses a NAPOT PMP region and emits
a store or load which will cross the boundary of that region at either
the top or the bottom.
When a writeback exception occurs when the instruction in ID/EX has seen
an instruction fetch error we need to ensure that error doesn't get
notified to cosim. This requires watching for a writeback exception and
removing the latest iside error from the queue if needed.
This refactors the code to avoid a -1 index access that caused no issues
in functional verification but caused lint errors and is problematic for
formal tools.
Fixes#1799
Coverpoints for priv modes with interrupts and mstatus.MIE, and with exceptions.
Also, fixed a checker for scenarios when interrupt is taken from lower priv modes.
Signed-off-by: Saad Khalid <saad.khalid@lowrisc.org>
When Ibex does a load that receives data with bad integrity it
suppresses the write to the destination register. The implements
matching functionality for cosim.
This commit is mainly an extension to cosim environment to drive the newly
introduced state variable `nmi_int` in Spike.
This commit
- Extends RVFI interface by a single bit (ext_nmi_int)
- Configures cosim to set nmi_int inside Spike
Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
This test picks between inserting an integrity error or a bus error
to the response in the case of a memory request from Ibex. Introduces
a control knob `enable_mem_intg_err` which can control the rate of
having integrity errors per request.
This commit also disables checking for double fault alerts in the
scoreboard because they're expected to be seen while simulating and
they don't cause infinite loop problems because every time a memory
response is requested the error causing part is just randomized.
That means Ibex trying to execute same instruction again would have
a chance to succeed this time.
Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
This enables the sequence to corrupt the integrity on write responses
should it choose to. Previously the driver would always produce correct
integrity.
