This commit makes sure that whenever Vivado is used, the Verilog
define `FPGA_XILINX` is set. This define can be used to enable Xilinx
specific pragmas in the RTL code. It is currently used to implement
the performance counters with DSP slices (incl. integrated output
registers for counter widths <= 32) which helps to save logic resources
and FFs (-7% and -15% when using e.g. 10 counters).
Previously, we had to set this parameter in every single top-level .core
file using Ibex.
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
- Add a major and minor alert output which can be used by the system to
react to fault injection attacks
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
Use Xilinx-specific implementations for primitives, such as RAM and the
clock gate (which will now be implemented using a BUFGCE macro, and no
longer with a latch).
Verified in Vivado synthesis to pick up the Xilinx primitive now.
