Currently the Ibex run scripts return 0 no matter what the test result
is.
To get Ibex sims correctly integrated into CI, the Makefile needs to
return 1 upon seeing a log comparison failure to indicate an error.
Signed-off-by: Udi Jonnalagadda <udij@google.com>
Add parameter `DbgHwBreakNum` to configure the number of HW breakpoints.
The parameters controls the number of trigger registers available if
debug support is enabled with `DbgTriggerEn`.
Closes#1070
- This field is read-only to software, and so should retain its previous
value on a write. This fixes#1134.
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
- This change should have no functional impact on the design
- Adding the separate module will allow easy parameterization
of security hardening for individual CSRs in the future
- As a side benefit, clock gating is added for CSRs that didn't
previously have it
- Note that this change makes the cpuctrl register always present,
rather than individual bits being added depending on parameterized
features. This is not ideal, but the parameterization becomes rather
messy otherwise.
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
- Document that SecureIbex cannot be used without a multiplier and add
an assertion in the rtl. This fixes#1080.
- Move the PC checking hardware onto its own parameter to match all the
other individual security features.
- Make the PC increment behavior more sensible on fetch errors (and make
it match the icache behavior). Factor this into the PC increment check
to prevent false triggering, fixes#1094.
- Stop the PC mismatch checker firing on dummy instructions, fixes
#1095.
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
- Without the B extension, a gorci instruction should decode as an
illegal instruction.
- Relates to #1129
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
Option to control the state of the Ibex tracer.
Defaults to enable, but allows a setting to disable the trace log.
In long running simulations this file can get quite big and the contents
might not be needed. Use the argument `+ibex_tracer_enable=0` to prevent
the creation of the file.
The documentation restructure in #1119 resulted in a new URL for the
documentation on Ibex system examples. This commit updates the in-tree
link to reference that new URL.
Signed-off-by: Alex Bradbury <asb@lowrisc.org>
Restructure the existing documentation to group the content by intended
audience. This produces four sections:
* An introduction section, relevant to "newcomers" to Ibex.
* An user guide, intended for hardware designers (integrators) and
software developers who want to integrate Ibex, and develop software
for it.
* A reference guide, which provides background information on the
design. This section is essential when working on Ibex, and also
documents our design decisions.
* A developer guide aimed at people modifying Ibex itself. It consists
mostly of process and tool documentation: how to run the verification
after a code change, how to use GitHub, etc.
This commit is large, but text is mostly unchanged. A couple of
introductions and tables of content were added, but no significant
changes to the text have been made. These will be done in follow-ups.
Signed-off-by: Philipp Wagner <phw@lowrisc.org>
Adding the "small" sections to the example linker script. This ensures
that all sections of memory needing to be zeroed are captured.
Fixes#1092
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
At some point in the future, the version of binutils we're using, and
the released version of LLVM, will coincide to use the correct name. In
the meantime, this change just uses the number which is supported by
both compilers.
This is, as I understand it, the only stumbling block to compiling the
in-repo C benchmark code with both GCC and LLVM. Being able to do so
would make it much easier for us to do comparisons on the benchmarks for
both compilers.
Signed-off-by: Sam Elliott <selliott@lowrisc.org>
Check that the number of cycles are always as specified for the current
configuration for data independent operations.
The required input signals for each arithmetic operation are split into
different files which are included into the testbench.
For each combination of operation and configured configuration
(slow/fast/single) a define stores the number of cycles in a separate
file. A target exists for each combination.
For a convenient execution the targets are grouped together in a
makefile.
The implementation is based on the formal/icache checks.
For the selection of the single cycle multiplication with the fast
multiplication the parameter is set directly to the enum integer value.
- If there is a request to enter debug mode (either due to a halt
request or single stepping mode) on the same cycle as an EBREAK
instruction, continue with the EBREAK and capture the ID PC rather
than the IF PC.
- relates to #1106
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
Some sequences run in "no invalidate" mode. Unfortunately, sometimes
we *have* to invalidate, either because we have a stale seed, or
because we're at the start of a sequence.
It turns out that "no invalidate" is a soft requirement, so we can
weaken it here. This patch also renames the flag to
"avoid_invalidation" to make it clear that this is allowed to be
violated occasionally.
Closes#1101.
The PR that I pushed up to add sby support to
Edalize (https://github.com/olofk/edalize/pull/173) ended up with a
different input format from the one it started with.
That's now merged into master, so this patch updates the Ibex code to
match the final syntax.
There's a long and painful discussion on the setuptools issues
list (I count 9 issues raised the day after the release). This is all
to do with how Debian/Ubuntu installs stuff with pip.
There's an "official" workaround that involves setting things in your
environment, but that looks a bit fiddly with the Azure pipelines
stuff and this has been such a disaster that I'm pretty certain the
setuptools maintainers will release something more sensible soon.
See e.g.
https://github.com/pypa/setuptools/issues/2350#issuecomment-683512526
for a careful description of what's going on.
- The core does not rely on instr_err_i being always valid, and most bus
protocols don't support that
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
Currently in ibex_controller.sv when generating the ID of any fast
interrupts, irq_fast[5] is checked for twice.
This is a redundant line, and so this PR simply removes it.
Signed-off-by: Udi <udij@google.com>
The ci/azp-private.yml file is a skeleton and only used to trigger an
Azure Pipelines run which integrates into the ibex repository. All real
job description is in a private repository for licensing reasons.
Put all build dependencies into a CI-specific script
(ci/install-build-deps.sh). No effort has been made to make this script
suitable for non-CI users.
Add a script to convert the contents of ci/vars.yml to Azure Pipelines
logging commands, which effectively set runtime variables in a pipeline.
We need this script as a workaround for a missing Azure Pipelines
feature: variables are not inherited in extended templates, and reading
the vars.yml file in a "extends" template isn't possible either (at
least not if we want to use the exact revision of the ibex repository
which triggered CI).
PRJ_DIR is presumably meant to point to the root of the git repository;
instead, it was pointing one directory higher up in the hierarchy. This
worked as long as the repository was checked out into a directory called
"ibex" -- but not otherwise, as in CI.
This commit replaces the previous combination of `RV32M` bit parameter
used to en/disable the M extension and the `MultiplierImplementation`
used to select the multiplier implementation by a single enum parameter.
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
Vendor in some updates to PMP test generation.
Update code from upstream repository https://github.com/google/riscv-
dv to revision 17d79847e376a591cb3dcaae7601c98b0e70e8ac
* Update pygen/pygen_src/isa/riscv_cov_instr.py (Hodjat Asghari
Esfeden)
* Minor issues fixed in the functional coverage flow (Hodjat Asghari
Esfeden)
* fix pmp offset constraint (Udi Jonnalagadda)
* Fix minor issues (aneels3)
* - Adds riscv_instr_cover_group file with a few covergroups -
Confirms riscv_instr_cov_test script is up and running fine -
Initializes the registers to 0 during their first gpr_state access
(for ovpsim output log) (Hodjat Asghari Esfeden)
* update directed pmp sequence constraint (Udi Jonnalagadda)
* remove unreachable if...else statement (Udi Jonnalagadda)
* update post_process() (aneels3)
* add ecall_handler (aneels3)
* Fix post_process() issue (aneels3)
* Fix typo in post_process (aneels3)
* Completed riscv_cov_instr class (decoupled from riscv_instr_cov_test
file) Added private _riscv_cov_instr module to manually retrieve
format/category/group/imm_t based on the name of the instruction
(Hodjat Asghari Esfeden)
* add post_process() (aneels3)
Signed-off-by: Udi <udij@google.com>
The shortlog from the vendor tool's automated patch is reproduced at
the bottom of this commit message.
The automated commit is squashed with one to update how we depend on
bus parameters. Before, we had to provide an "Ibex top package". This
behaved the same as OpenTitan's "lowrisc:constants:top_pkg", but
avoided having to vendor in that file.
On the OpenTitan side, this has been tidied up with commit
d266c68 ("[dv] Update dv_utils sources to use bus_params_pkg"). This
changes the dependency of dv_utils to
"lowrisc:opentitan:bus_params_pkg". We still have to provide our
own (now called "lowrisc:ibex:bus_params_pkg") and need to patch the
dv_utils dependency, but this is a bit cleaner because dv_utils is
less likely to accidentally include dependencies on OpenTitan
internals.
On our side, we have to update the vendoring patch for dv_utils (and
change its name). We also need an equivalent patch for dv_lib. Then we
rename our hacky "Ibex top package" to "bus_params_pkg". The ICache DV
environment also needs patching to use the bus parameters properly.
Phew!
* [dv] Update prim_present cov opt (Srikrishna Iyer)
* [dv] Align VCS and Xcelium cov var names (Srikrishna Iyer)
* [dv] Split coverage for functional and auto tests (Srikrishna Iyer)
* [dvsim] Do builds smartly (Srikrishna Iyer)
* [syn] Carry over synthesis flow updates from bronze (Michael
Schaffner)
* [dvsim] Lint cleanup (Srikrishna Iyer)
* [dvsim] Allow testplan to be omitted (Srikrishna Iyer)
* [dvsim] Address lowRISC/opentitan#3071 comments (Srikrishna Iyer)
* [dvsim] lint cleanup (Srikrishna Iyer)
* [dvsim] Add support for second-level indirection (Srikrishna Iyer)
* [dvsim] Change cores-root to avoid conflicts with autogen'd core
files (Michael Schaffner)
* [dvsim] Update `tests` key behavior in regressions (Srikrishna Iyer)
* [lint] Minor update of ERROR patterns in parser script (Michael
Schaffner)
* [packer] Revise the implementation (Eunchan Kim)
* [flow] Remove lint makefile (Timothy Chen)
* [flows] Various updates to tools and documents to suppose top/ip
select (Timothy Chen)
* [dv/shadow_reg] shadow_reg update error (Cindy Chen)
* [rtl/alert] change the naming from _en_i to _req_i (Cindy Chen)
* [dvsim] Tidy up config file loading in FlowCfg.py (Rupert Swarbrick)
* [dvsim] Make it simpler to derive from FlowCfg (Rupert Swarbrick)
* [lint] Update warning/error exclusions in parser scripts (Michael
Schaffner)
* [dvsim] Fix for `--tool` override (Srikrishna Iyer)
* [dvsim] Bug fix in LintCfg.py (Srikrishna Iyer)
* [prim/dv] Integrate LFSR TB with dvsim (Udi Jonnalagadda)
* [uvmdvgen] Update template to reflect bind reorg (Srikrishna Iyer)
* [dv] remove prim_lfsr_bind (Srikrishna Iyer)
* [dv] Cleanup lint warnings in csr_utils_pkg (Srikrishna Iyer)
* [dv] Cleanup lint warnings in clk_rst_if (Srikrishna Iyer)
* [dvsim] Fix coverage dashboard link (Srikrishna Iyer)
* [prim] Rename prim_util_memload.sv to svh (Philipp Wagner)
* [lint/doc] Update linting readme to reflect recent updates (Michael
Schaffner)
* [lint] Remove legacy Makefile flow for linting tools (Michael
Schaffner)
* [dvsim/lint] Enable Verilator lint in Dvsim (Michael Schaffner)
* [prim_arbiter_fixed/fpv] Add generated FPV testbench (Michael
Schaffner)
* [prim_arbiter_fixed] This adds a fixed priority arbiter (Michael
Schaffner)
* [prim] Domain-Oriented Masking AND logic (Eunchan Kim)
* [dv] Update dv_utils sources to use bus_params_pkg (Srikrishna Iyer)
* [dv] Update mem_model to use bus-params_pkg (Srikrishna Iyer)
* [dv] Update dv_lib sources to use bus_params_pkg (Srikrishna Iyer)
* [uvmdvgen] Support for setting vendor name in VLNV (Srikrishna Iyer)
This signal aimed to ensure loads/stores completed succesfully when an
interrupt or debug request appeared at the same time they were being
executed when the writeback stage is present. However other stall logic
suffices for this purpose (debug/interrupt will wait for instruction to
unstall in ID/EX which only happens once request has been sent out, then
first instruction of debug/interrupt handler will stall until load/store
response has been seen based on the generic stall logic for lsu requests
in the writeback stage).
With this signal in place debug single stepping was broken around loads
and stores.
Fixes#1029
- Add a technology map for latches (only works with nandgate45 library
at the moment)
- Add a real latch-based clock gating cell
- Update timing path reporting to differentiate between register and
latch paths
- Update summary results in README to reflect the latch-based numbers,
plus add numbers for a micro-riscy-style (RV32EC) config
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
