Verible lint now supports waivers without regex and line arguments. Use
this new feature and remove the workaround we had in place.
Signed-off-by: Philipp Wagner <phw@lowrisc.org>
This PR updates the `implemented_csrs` list in `riscv_core_setting.sv`
and adds the two custom CSRs `cpuctrl` and `secureseed` to the
`custom_csrs` list. Both are for use by the riscv-dv generator.
Signed-off-by: Udi <udij@google.com>
This removes the manually copied version at dv/uvm/core_ibex/common
and vendors things properly now that the vendor tool supports such
things (this picks up the same OpenTitan version as the previous
commit: lowRISC/opentitan@067272a2).
Update code from upstream repository
https://github.com/lowRISC/opentitan to revision
067272a253f4eeed4ae58a9171ee266256528117
* [dv/common] initial support for shadow register (Cindy Chen)
* [rtl/prince] Small fixes for PRINCE cipher logic (Udi Jonnalagadda)
* [dv doc] Fix rendered testplan table (Srikrishna Iyer)
* [prim/dv] Enable coverage collection for PRESENT (Udi Jonnalagadda)
* [dvsim/syn] Minor fix in message reporting (Michael Schaffner)
* [prim] Make prim_clock_inverter a tech specific prim (Michael
Schaffner)
* [vsg] fix _i/_o for several modules (Scott Johnson)
* [doc] Update Licence Headers to fit agreed style (Sam Elliott)
* [vsg] fix _i/_o usage on sram_arbiter (Scott Johnson)
* [vsg] fix _i/_o usage on prim_fifo (Scott Johnson)
* switch to host, primary, or over-arching as appropriate (Scott
Johnson)
* [dvsim/lint/syn] Properly set the errors_seen value to return
nonzero status (Michael Schaffner)
* [dvsim] Fix open() call with Pathlib for older Python versions
(Michael Schaffner)
* [style-lint] Last round of minor fixes to get all targets clean
(Michael Schaffner)
* [prim] Add shadow register primitive (Pirmin Vogel)
* [flash_ctrl] Cosmetic updates enum literals (Srikrishna Iyer)
* [tool/script] delete clean section in make files (Cindy Chen)
* [dvsim] Add git commit and branch info to reports (Michael
Schaffner)
* [dvsim/syn/lint] Add options to selectively sanitize reports
(Michael Schaffner)
* [lint] Update waiver file for prim_generic_pad_wrapper (Michael
Schaffner)
* [prim_pad_wrapper] Update pad wrapper (Michael Schaffner)
* [alert_handler/rtl] priority between ping_ok and sig_int_err (Cindy
Chen)
* [prim] Add a few prim cells needed for clock / resets (Timothy Chen)
* [dv] added default timeout message to DV_SPINWAIT (Srikrishna Iyer)
* [dv] Add mechanism to configure vseq via knobs (Srikrishna Iyer)
* Make the wmask assertion in prim_generic_ram_*p only apply to writes
(Rupert Swarbrick)
* [prim_gate_gen] Recalibrate gate generator for new std cells
(Michael Schaffner)
* [primgen] Use SafeDumper for YAML (Philipp Wagner)
* [primgen] Fix some flake8-reported style issues (Philipp Wagner)
* [prim] Improve extraction of parameter port list (Philipp Wagner)
* [prim] Remove outdated comment from primgen (Philipp Wagner)
* Added missing include prim_assert.sv (Dawid Zimonczyk)
Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
This fixes a test failure that I was seeing when following a "many
errors" test by something different. To reproduce,
make -C dv/uvm/icache/dv \
SEED=1465832714 \
TESTS=ibex_icache_stress_all_with_reset
There are actually two different ways this can come unstuck:
(1) Memory request goes out and gets put into the response queue.
req_i goes low. Sequence changes. req_i goes high and we get the
response from the previous request (but mem_err_shift has changed
in the meantime).
To fix this, we pair up the memory seed and its associated
mem_err_shift in the scoreboard queue, rather than retrieving
mem_err_shift from the config object when the response comes in.
(2) Memory request goes out. Sequence changes. Memory request is
handled (with new mem_err_shift). Scoreboard sees the result. New
sequence generates its first item.
In this case, the scoreboard will expect the old mem_err_shift and
see the new one. To fix this, we add an extra entry to the list of
valid states in the scoreboard if needed so that we also check the
mem_err_shift currently in the config object.
You might worry about what happens if we have two back-to-back
sequence changes that change mem_err_shift without ever changing seed:
what happens if we have a situation like (1), but for the "middle"
sequence. To avoid this problem, we actually add the extra entry in
the fix for (2), so it will look like a new seed arrived as part of
the middle sequence, so long as we have read at least one
result (always true in the core sequence).
This now allows you to specify how many seeds to run. Sadly, you can't
say "give me 10 seeds, starting at 1234" because dvsim doesn't support
that at the moment. But it does at least avoid quite such long command
lines.
Instead of:
../../../../vendor/lowrisc_ip/dvsim/dvsim.py \
ibex_icache_sim_cfg.hjson \
--scratch-root ../../../../build \
--reseed 5 \
-c
you can run:
make RESEED=5 COVERAGE=1
We now have a clock/reset interface and the dv_utils stuff vendored
from OpenTitan so can delete the duplicates and point the file list at
the vendored files.
The only difficulty is that the clock interfaces are slightly
different, so there are a couple of minor changes to the core_ibex
test lib, renaming "clk_if" to "clk_rst_if" and changing how we apply
resets.
Note that the testbench (core_ibex_tb_top.sv) starts the clock and
resets the DUT at the start of time. This is different from how other
OpenTitan VIP does things (where the reset happens in the sequence),
but this is the smallest change I could make from how it worked
before (where the reset happened in the clock interface itself).
The idea is that this can supply top_pkg.sv, a top-level thing in
OpenTitan, for DV code we vendor from there. It's probably better to
do this than to directly vendor in OpenTitan's top_pkg, because the
latter has information about e.g. flash memory layout, which doesn't
really have any meaning for Ibex.
cov_report_page is used by dvsim's SimCfg.py to print a message to the
console with the path to the dashboard HTML page. Most of these
messages have the full path (useful for copy-pasting), but this one
didn't.
This is essentially a duplicate of OpenTitan PR 2934[1] (because we're
not able to vendor these files properly yet).
[1] https://github.com/lowRISC/opentitan/pull/2934
As pointed out by @tomroberts-lowrisc in #983, the current
implementation of riscv_debug_single_step_test cannot handle
single-stepping over instructions that change the PC.
This PR aims to introduce this functionality, utilizing the
new instr_monitor_if.
Now, if the core single-steps onto a branch/jump instruction, the
testbench will log the new target PC and compare it against the actual
target address stored in `dpc`.
"Normal" instructions are checked as usual by incrementing the
instruction's PC by either 2 or 4 (depending whether it is compressed)
and comparing that against `dpc`.
Previously, these bits were not checked when decoding slli, srli and
srai, causing some illegal instruction encodings not to trigger an
illegal instructions exception.
This resolveslowRISC/Ibex#1018.
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
This PR modifies the Ibex DV environment to use request/response
terminology instead of the current outdated naming scheme.
These changes are purely aesthetic.
- Add SECDED ECC checking to the register file when SecureIbex is
enabled
- No correction is attempted, but an alert is raised for the system to
intervene
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
- Add a major and minor alert output which can be used by the system to
react to fault injection attacks
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
But if you are using precompiled UVM it may be compiled with other timescale depending on compilation option used when it was compiled or tools default timescale value (uvm does not set timescale int the code).
In this case for us precompiled UVM timescale is 1ps/1ps - so UVM gets 1000000000 in set timeout but interprets it as ps. As a result timeout is 1000 times smaller that you expect. That is why we are getting timeouts.
It is hard to find perfect solution. One of them is to recompile the UVM with -timescale 1ns/ps (or whatever you will use for your design).
Fix a lint error reported by AscentLint:
```
E ALWAYS_SPEC: ibex_counter.sv:59 Edge triggered block may be more accurately modeled as always_ff New
```
* Mention the need to install `libelf-dev`. Thanks to Bert Pieters for
reporting this.
* Guide users to install our Python dependencies, including fusesoc and
edalize, from `python-requirements.txt`, to ensure they have the
right version.
* Prefer ELF files for Verilator simulations. This makes it easier to
use existing ELF files from another software build system.
Fixes#1019
We previously had a dependency on all primitives in Ibex, even though we
only depend on the LFSR primitive. Now that there's a more fine-grained
dependency available, we can use that.
This has the great benefit of restricting all lint tools to only the
code we're interested in, and not linting all primitives in OpenTitan
together with Ibex. This also helps tools like yosys, which aren't able
to parse all of OpenTitan's code yet.
Update code from upstream repository
https://github.com/lowRISC/opentitan to revision
ebf4663b42a9d81d026db5821b5c8249d54f23a7
* [prim_lfsr] Fix description in core file for FPV (Philipp Wagner)
* [prim_lfsr] Factor out into a separate core file (Philipp Wagner)
Signed-off-by: Philipp Wagner <phw@lowrisc.org>
As a result of lowRISC/opentitan#2405 and lowRISC/ibex#928 (reporting
that interrupts that came in while a load instruction was in the ID
stage caused some incorrect behavior in Ibex), this PR adds some new
directed interrupt and debug tests to check that the core behaves
properly during execution of each supported instruction when some
external irq/debug stimulus comes in.
To do this, we use the two new functions `decode_instr(...)` and
`decode_compressed_instr(...)` in `core_ibex_test_list.sv` to "decode"
every instruction that the `core_ibex_instr_monitor_if` sees in the ID
stage of the pipeline. Once the testbench decodes an instruction that
we have not seen before, it can then drive interrupt or debug stimulus
into the core.
Once any given instruction has been detected by the testbench (and
stimulus driven), it will no longer drive stimulus if this instruction
is seen in the decode pipeline (e.g. if we have previously detected a
`c.addi` instruction in the ID stage and have driven irq/debug stimulus,
we will no longer drive stimulus if we see another `c.addi` instruction,
no matter the operands). This is to avoid driving irq/debug stimulus
after every single instruction as this will add a huge unwanted amount
of simulation latency.
A few notes:
- We drive irq/debug stimulus into the core every time we see a
`wfi` instruction, as otherwise we will timeout as the core waits
infinitely for some stimulus from the outside world.
- We ignore some system-level instructions (ebreak/mret/dret) and
illegal instructionsfor now, as driving stimulus during these
instructions will result in a nested trap, which requires special
handling.
- The interrupt agent was modified slightly to drive stimulus by
default on the falling edge of the clock, so this way we can "catch"
instructions that are in the ID pipeline for only a single cycle.
- The duration for which the testbench raises `debug_req_i` for the core
is also increased to avoid edge cases where we lower the debug line
too early (e.g. while long multicycle instructions like `div` are
executing in the ID stage).
Update code from upstream repository
https://github.com/lowRISC/opentitan to revision
9ac4f9c8b924b79eb7d3581b29346a612f705751
* Allow verilated top-levels to do work after a simulation completes
(Rupert Swarbrick)
* Add some missing dependencies on lowrisc:prim:assert (Rupert
Swarbrick)
Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
Use Xilinx-specific implementations for primitives, such as RAM and the
clock gate (which will now be implemented using a BUFGCE macro, and no
longer with a latch).
Verified in Vivado synthesis to pick up the Xilinx primitive now.
Support for this extension is not experimental (it's fully verified using
RISCV-DV) but the extension might change before being ratified.
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
- The "PINCONNECTEMPTY" waiver is part of our normal waiver file, no need
to add it to the tool invocation.
- Recent versions of Verilator choose good defaults for MAKE_OPTS,
passing it explicitly overrides the settings.
- All Verilator code is now lint clean, we can remove `-Wno-fatal`.
- FST traces are not much slower then VCD traces any more in recent
Verilator versions, remove the respective comment.
- Align comment about the compile/sim time for tracing with other files
and OpenTitan.
The clock gating primitive is now a dependency of the
lowrisc:ibex:ibex_core file directly and only used in there, we can
remove it from the simulation or FPGA dependency collections.
The only core which needs lint waivers is ibex_core.core; it will then
inherit those waivers to other cores, such as ibex_core_tracing.core,
and higher-up users of these cores (such as the simple system).
Also remove the Verible lint configuration, which happens to be the
default by now. This fixes#736 by making it unnecessary.
The lint target in ibex_core_tracing was used to also lint unrelated
files which are needed for some simulations (e.g. the simple system).
Remove them from there, as they really don't belong there.
Ibex depends on a clock gating primitive. This has always been the case;
previously, we have under-specified the dependency list by simply not
including this dependency. This is problematic not only because "IT'S
WRONG!", but also because it breaks self-contained targets, like
Verilator lint, which cannot run on ibex_core or ibex_core_tracing
without having a way to find the clock gating primitive.
