Update code from upstream repository https://github.com/google/riscv-
dv to revision 5b1dd4e2eb11d49d3275da80953efc0c50f90447
* Add compliance mode to coverage model (google/riscv-dv#361)
(taoliug)
* Revert " Make assign_operand become a method of class
RiscvInstructionTraceEntry (google/riscv-dv#357)" (google/riscv-
dv#360) (taoliug)
* Fix script issue (google/riscv-dv#358) (taoliug)
* Make assign_operand become a method of class
RiscvInstructionTraceEntry (google/riscv-dv#357) (Hai Hoang Dang)
* Remove unused variable (google/riscv-dv#348) (Hai Hoang Dang)
* Functional coverage improvement (google/riscv-dv#356) (taoliug)
* Fix list access exception thrown when parsing ovpsim illegal
instruction (Udi Jonnalagadda)
* Add compliance mode and RTL mode to the coverage model
(google/riscv-dv#354) (taoliug)
* Fix lr/sc sequence (google/riscv-dv#353) (taoliug)
* Fix minor illegal instruction issue (google/riscv-dv#351) (taoliug)
* Migrate to new instruction class (google/riscv-dv#350) (taoliug)
* misc issue fixes (google/riscv-dv#349) (taoliug)
* Update README to add contact info for the collaboration request
(google/riscv-dv#347) (taoliug)
* Support running specific multiple tests (google/riscv-dv#346) (Hai
Hoang Dang)
* Fix rv64 coverage model issue (google/riscv-dv#344) (taoliug)
* Fix the link for yaml/base_testlist.yaml (google/riscv-dv#343) (Hai
Hoang Dang)
* refactor debug ROM generation (Udi Jonnalagadda)
* Add a runtime option to run with experimental features
(google/riscv-dv#341) (taoliug)
* Fix a few issues with the new instruction class (google/riscv-
dv#340) (taoliug)
* Improve performance of new experimental instruction class
(google/riscv-dv#339) (taoliug)
* Fix CSR randomization bug when generating loops (google/riscv-
dv#337) (udinator)
* Add support coverage flow for qrun, and minor fix for cov.py
(google/riscv-dv#335) (Hai Hoang Dang)
* [ovpsim] Coding style fixes, fix floating point compare mismatch
(google/riscv-dv#334) (taoliug)
* Fix ius flow issue (google/riscv-dv#333) (taoliug)
* Fix a few new instruction class issues (google/riscv-dv#332)
(taoliug)
* Added two includes and starting variables for adding bitmanip
extension (google/riscv-dv#328) (simond-imperas)
* Integrate experimental instruction class (google/riscv-dv#331)
(taoliug)
* Minor fixes to run.py (google/riscv-dv#330) (taoliug)
* Run.py: minor refactor the code for compile, and simulate
(google/riscv-dv#326) (Hai Hoang Dang)
* Add requirements for install dependencies (google/riscv-dv#325) (Hai
Hoang Dang)
* Adding support qrun simulator (google/riscv-dv#324) (Hai Hoang Dang)
* Add new experimental instruction class (google/riscv-dv#323)
(taoliug)
* Added command line control of coverage and added hooks for vector
coverage development (google/riscv-dv#317) (simond-imperas)
* Fix compilation issue (google/riscv-dv#322) (taoliug)
Signed-off-by: Udi <udij@google.com>
- Add the minimum amount of trigger system to support GDB hbreak
- Only a single trigger is implemented
- Only instruction address matching
- Only break into debug mode (no native debug)
- Fixes#382
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
The VerilatorSimCtrl class was always intended to be used only once in
an application, since it sets up a global signal handler and needs to be
accessible from DPI modules. This accessibility was achieved through a
global variable `simctrl`.
With this commit the VerilatorSimCtrl is switched to a singleton class.
The instance is accessible through `VerilatorSimCtrl::GetInstance()`.
The downside of that approach is that we loose the constructor
arguments, and need to deal with a class which potentially hasn't top or
the clock and reset signals set.
This PR includes the following:
- add script syn_yosys.sh, which runs sv2v and yosys for ibex_core
- add example std. cell lib cmos_cells.lib (copied from yosys repo)
- add dummy prim_clock_gating.v module
- add initial yosys synthesis script syn.ys
All functions in simutil_verilator return booleans to indicate
success/failure, where 1 == true, and 0 == false.
simutil_verilator_set_mem() returns an int due to DPI interface
restrictions. Before, 0 meant success, and 1 meant error.
To keep things nice and consistent, turn things around and align with
the bool meaning.
Support initialization of memory by loading content from ELF files.
All segments of the ELF file with the type `PT_LOAD` are merged into a
temporary buffer and then forwarded to a predefined memory.
This is an addition for setting the memories with VMEM files.
Memories must implement `simutil_verilator_set_mem` to support the
setting of values with a width of 32 bits. A return value of 0 must
indicate a successful operation and 1 an error.
Memories are defined by a call to `RegisterMemoryArea()` before the
execution of the simulation, at which point the arguments are parsed and
the initialization is started. The memories are identified by unique
name. The design specific location is used to set the SystemVerilog
scope.
Registered memories can be printed by using `-l list`. The unique name
is used for `-l name,file.elf` together with the file path.
An optional part of the argument is the type of the file, `elf` or
`vmem`, and if not provided it is attempted to detect the type by
looking at the file extension.
The memory specific arguments which already existed accept now also ELF
files. They use predefined names and are included to keep the interface
stable.
Contents of an ELF segment which has a bigger memory size than file size
are not set. This is typically required for BSS sections for zero-ing
the memory.
- Switch from Makefile calling fusesoc to fusesoc calling Makefile
- Pass parameters through DPI rather than as env variables
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
Instead of copying the commands from the documentation or using the
shell history to find the commands use a Makefile as a convenience to
run some common tasks.
A shell's completion system can make use of the targets and provide tab
completion.
In debug mode, exceptions shall not update any CSRs including `mcause`,
`mepc`, `mtval`, `dpc` and `mstatus`, see Debug Spec v0.13.2, p.39.
This resolveslowRISC/ibex#168.
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
All CSR addresses supported by the TB are now delared as an X
macro list. This list is then used to autogenerate the enum
type, string print helper and an array of all addresses.
The array of addresses can now be used by the randomize generator
to turn an arbitrary integer index into an address. This removes
the restriction on only generating contiguous address ranges noted
in #443.
Add missing signal csr_restore_dtret_i
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
This commit removes a copy of the dummy clock gating primitive from
tree previously used for UVM-based DV. There is another, identical copy
of the same primitive in `shared/rtl` that can be used instead.
This resolveslowRISC/ibex#213.
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
This commit modifies the assertions to not fire as long as the reset
is active. Also, it updates some assertions.
This resolveslowRISC/ibex#274.
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
Move Xilinx specific code into shared folder so it can be re-used by
different examples.
Use the shared RAM code and make use of byte enable signal.
Fixeslowrisc/ibex#144
