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Author	SHA1	Message	Date
Markus Wegmann	a2f4e65e6c	Fix clock extraction	2017-01-08 23:10:35 +01:00
Markus Wegmann	659e234be0	Rename reg buffer signals	2017-01-08 11:57:45 +01:00
Markus Wegmann	099673de2b	Do not ungroup	2017-01-08 11:42:37 +01:00
Markus Wegmann	23eda1d0f0	Patch python script	2017-01-08 11:29:05 +01:00
Markus Wegmann	25273056f0	Fix	2017-01-08 10:58:51 +01:00
Markus Wegmann	4f71899e93	fix	2017-01-08 03:17:33 +01:00
Markus Wegmann	98c47b59bd	Fix	2017-01-08 03:02:02 +01:00
Markus Wegmann	4f3d647a1d	Fix	2017-01-08 02:59:27 +01:00
Markus Wegmann	9f3cd88c4f	Remove unnecessary signal	2017-01-08 02:37:50 +01:00
Markus Wegmann	82c0250a63	Try fix	2017-01-08 02:23:44 +01:00
Markus Wegmann	4494615afa	Try fix	2017-01-08 02:19:39 +01:00
Markus Wegmann	c39e9e4f26	Only change state of register buffer if a valid instruction is present	2017-01-08 01:58:03 +01:00
Markus Wegmann	d7631c3152	Fix flipflop logic of buffer regs	2017-01-08 01:07:09 +01:00
Markus Wegmann	fc0bf251d8	Fix syntax	2017-01-08 00:50:39 +01:00
Markus Wegmann	60457ff557	Fix syntax	2017-01-08 00:49:18 +01:00
Markus Wegmann	7de6ba7afc	Fix syntax	2017-01-08 00:46:53 +01:00
Markus Wegmann	9c5903dbc6	Add register buffers for ID in MERGE_ID_EX	2017-01-08 00:42:17 +01:00
Markus Wegmann	22eaa4968a	Fix syntax	2017-01-07 23:13:16 +01:00
Markus Wegmann	88082be246	Fix syntax	2017-01-07 23:12:23 +01:00
Markus Wegmann	f5870569b5	Try to integrate misaligned access in small pipeline case	2017-01-07 23:09:19 +01:00
Markus Wegmann	89a313f003	Modify tracer for support with MERGE_ID_EX	2017-01-07 22:01:38 +01:00
Markus Wegmann	8081065e18	Remove potential time loop	2017-01-07 21:34:20 +01:00
Markus Wegmann	4a048874e0	Fix syntax	2017-01-07 21:01:51 +01:00
Markus Wegmann	249cf9ca4d	Rewrite controller for MERGE_ID_EX	2017-01-07 20:59:22 +01:00
Markus Wegmann	413fbccff2	Remove assert	2017-01-07 19:34:28 +01:00
Markus Wegmann	28778ff494	Fix syntax	2017-01-07 19:13:52 +01:00
Markus Wegmann	7a63a0dd0c	Maybe fix time loop in ID	2017-01-07 19:11:55 +01:00
Markus Wegmann	d83a6d8813	Add RV32E assertion warning	2017-01-07 17:36:15 +01:00
Markus Wegmann	e76d5b44a6	Try to break time loop in merged ID-EX	2017-01-07 17:04:47 +01:00
Markus Wegmann	cc4d434fb7	Remove pc_ex from port map (MERGE_ID_EX)	2017-01-07 16:47:52 +01:00
Markus Wegmann	7ee4f09703	Fix wrong config in load_store_unit	2017-01-07 16:39:58 +01:00
Markus Wegmann	e3787b2c7f	Fix syntax	2017-01-07 16:36:58 +01:00
Markus Wegmann	909ad7d416	Fix default configuration	2017-01-07 16:33:14 +01:00
Markus Wegmann	5fdadb7a4d	Remove non-used signal in Prefetcher	2017-01-07 16:26:42 +01:00
Markus Wegmann	f7820757e5	Fix syntax in ID	2017-01-07 15:51:35 +01:00
Markus Wegmann	d6f806cf84	Reformat prefetch_buffer_small.sv	2017-01-07 14:58:54 +01:00
Markus Wegmann	a0b0b764e4	Fix syntax in load_store_unit.sv	2017-01-07 14:40:30 +01:00
Markus Wegmann	840deaf241	Reformat id_stage.sv	2017-01-07 14:37:12 +01:00
Markus Wegmann	021dfd6721	Merge ID and EX with MERGE_ID_EX	2017-01-07 14:33:33 +01:00
Markus Wegmann	0b180fc637	Fix last	2017-01-07 14:32:37 +01:00
Markus Wegmann	704ee95373	Fix syntax last	2017-01-07 14:27:51 +01:00
Markus Wegmann	bd9000bd9b	Assert and test for non-compressed misaligned instructions in case of ONLY_ALIGNED	2017-01-07 14:24:46 +01:00
Markus Wegmann	e287d3fad1	Fix syntax	2017-01-07 11:57:14 +01:00
Markus Wegmann	f6941be2c5	Fix	2017-01-07 11:55:13 +01:00
Markus Wegmann	c8aa6f9ed2	Fix syntax	2017-01-07 11:53:43 +01:00
Markus Wegmann	69fc1a2e67	Begin to implement ID-EX merge	2017-01-07 11:52:03 +01:00
Markus Wegmann	42f73781d0	Add handling for NO_JUMP_ADDER in prefetcher	2017-01-07 10:49:56 +01:00
Markus Wegmann	ca6fd4faad	Handle branch_in_ex in case of splitted adder	2017-01-06 18:07:56 +01:00
Markus Wegmann	0ef801ae67	Fix bug when splitted adder was not finished when writing back return address in JAL	2017-01-06 17:23:39 +01:00
Markus Wegmann	29a4967ec9	Fix jump when splitted adder not ready	2017-01-06 16:46:39 +01:00