But if you are using precompiled UVM it may be compiled with other timescale depending on compilation option used when it was compiled or tools default timescale value (uvm does not set timescale int the code).
In this case for us precompiled UVM timescale is 1ps/1ps - so UVM gets 1000000000 in set timeout but interprets it as ps. As a result timeout is 1000 times smaller that you expect. That is why we are getting timeouts.
It is hard to find perfect solution. One of them is to recompile the UVM with -timescale 1ns/ps (or whatever you will use for your design).
Fix a lint error reported by AscentLint:
```
E ALWAYS_SPEC: ibex_counter.sv:59 Edge triggered block may be more accurately modeled as always_ff New
```
* Mention the need to install `libelf-dev`. Thanks to Bert Pieters for
reporting this.
* Guide users to install our Python dependencies, including fusesoc and
edalize, from `python-requirements.txt`, to ensure they have the
right version.
* Prefer ELF files for Verilator simulations. This makes it easier to
use existing ELF files from another software build system.
Fixes#1019
We previously had a dependency on all primitives in Ibex, even though we
only depend on the LFSR primitive. Now that there's a more fine-grained
dependency available, we can use that.
This has the great benefit of restricting all lint tools to only the
code we're interested in, and not linting all primitives in OpenTitan
together with Ibex. This also helps tools like yosys, which aren't able
to parse all of OpenTitan's code yet.
Update code from upstream repository
https://github.com/lowRISC/opentitan to revision
ebf4663b42a9d81d026db5821b5c8249d54f23a7
* [prim_lfsr] Fix description in core file for FPV (Philipp Wagner)
* [prim_lfsr] Factor out into a separate core file (Philipp Wagner)
Signed-off-by: Philipp Wagner <phw@lowrisc.org>
As a result of lowRISC/opentitan#2405 and lowRISC/ibex#928 (reporting
that interrupts that came in while a load instruction was in the ID
stage caused some incorrect behavior in Ibex), this PR adds some new
directed interrupt and debug tests to check that the core behaves
properly during execution of each supported instruction when some
external irq/debug stimulus comes in.
To do this, we use the two new functions `decode_instr(...)` and
`decode_compressed_instr(...)` in `core_ibex_test_list.sv` to "decode"
every instruction that the `core_ibex_instr_monitor_if` sees in the ID
stage of the pipeline. Once the testbench decodes an instruction that
we have not seen before, it can then drive interrupt or debug stimulus
into the core.
Once any given instruction has been detected by the testbench (and
stimulus driven), it will no longer drive stimulus if this instruction
is seen in the decode pipeline (e.g. if we have previously detected a
`c.addi` instruction in the ID stage and have driven irq/debug stimulus,
we will no longer drive stimulus if we see another `c.addi` instruction,
no matter the operands). This is to avoid driving irq/debug stimulus
after every single instruction as this will add a huge unwanted amount
of simulation latency.
A few notes:
- We drive irq/debug stimulus into the core every time we see a
`wfi` instruction, as otherwise we will timeout as the core waits
infinitely for some stimulus from the outside world.
- We ignore some system-level instructions (ebreak/mret/dret) and
illegal instructionsfor now, as driving stimulus during these
instructions will result in a nested trap, which requires special
handling.
- The interrupt agent was modified slightly to drive stimulus by
default on the falling edge of the clock, so this way we can "catch"
instructions that are in the ID pipeline for only a single cycle.
- The duration for which the testbench raises `debug_req_i` for the core
is also increased to avoid edge cases where we lower the debug line
too early (e.g. while long multicycle instructions like `div` are
executing in the ID stage).
Update code from upstream repository
https://github.com/lowRISC/opentitan to revision
9ac4f9c8b924b79eb7d3581b29346a612f705751
* Allow verilated top-levels to do work after a simulation completes
(Rupert Swarbrick)
* Add some missing dependencies on lowrisc:prim:assert (Rupert
Swarbrick)
Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
Use Xilinx-specific implementations for primitives, such as RAM and the
clock gate (which will now be implemented using a BUFGCE macro, and no
longer with a latch).
Verified in Vivado synthesis to pick up the Xilinx primitive now.
Support for this extension is not experimental (it's fully verified using
RISCV-DV) but the extension might change before being ratified.
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
- The "PINCONNECTEMPTY" waiver is part of our normal waiver file, no need
to add it to the tool invocation.
- Recent versions of Verilator choose good defaults for MAKE_OPTS,
passing it explicitly overrides the settings.
- All Verilator code is now lint clean, we can remove `-Wno-fatal`.
- FST traces are not much slower then VCD traces any more in recent
Verilator versions, remove the respective comment.
- Align comment about the compile/sim time for tracing with other files
and OpenTitan.
The clock gating primitive is now a dependency of the
lowrisc:ibex:ibex_core file directly and only used in there, we can
remove it from the simulation or FPGA dependency collections.
The only core which needs lint waivers is ibex_core.core; it will then
inherit those waivers to other cores, such as ibex_core_tracing.core,
and higher-up users of these cores (such as the simple system).
Also remove the Verible lint configuration, which happens to be the
default by now. This fixes#736 by making it unnecessary.
The lint target in ibex_core_tracing was used to also lint unrelated
files which are needed for some simulations (e.g. the simple system).
Remove them from there, as they really don't belong there.
Ibex depends on a clock gating primitive. This has always been the case;
previously, we have under-specified the dependency list by simply not
including this dependency. This is problematic not only because "IT'S
WRONG!", but also because it breaks self-contained targets, like
Verilator lint, which cannot run on ibex_core or ibex_core_tracing
without having a way to find the clock gating primitive.
Before we changed to vendoring in our RAM primitives from OpenTitan,
there was an SRAM_INIT_FILE define that you could stick in your core
file. That's now gone away, replaced by a parameter (MemInitFile). If
we want to plumb that in, we need to pass it properly through the
wrappers.
By now, ibex depends not only on the a clock gating cell, but also on
assert macros and a LFSR; there will be more to come. This removed piece
of documentation was from the early days, when only a clock gating cell
was to be provided (and we didn't ship one).
Today, users need to either use FuseSoC, or run fusesoc on the simple
system and "harvest" the resulting files if they want to copy-paste Ibex
into their build system. That's not ideal, but not something we can very
easily fix -- so let's remove the outdated documentation first to at
least reduce the confusion.
The waiver files currently don't support comments, and require the
"empty" regex; bugs have been filed to get that resolved upstream.
But beyond that, waivers are now functional.
Fix all remaining issues reported by Verible lint.
It turns out that #965 undid some of the fixes in `ibex_alu.sv`
that were done in #980 around the `SHUFFLE_*`/`FLIP_*` signals.
This turns out to be quite complicated, because the icache has a lot
of different counters that all track addresses or fill buffer state.
For an inductive proof to go through, you need to make the relations
between them explicit, which takes lots of assertions.
All of the signals defined in the formal_tb are prefixed with 'f_'.
This isn't strictly necessary, but it makes it much easier to see what
came from the design (since we are "bound in", our ports don't have _o
or _i suffixes).
We add a couple of protocol assumptions:
ICache <-> Core:
- Branch target addresses are half-word aligned
- The branch_spec signal is driven if branch is
ICache <-> Memory:
- The bus doesn't respond unless there is an outstanding request
- The bus doesn't grant more than 4 billion outstanding requests(!)
There's also some protocol state tracking:
- f_addr_valid tracks whether the ICache currently has an
architectural address. It goes high with branch_i (which gives the
cache an address) and goes low when the cache completes a
transaction with err_o set (since the data is bad, there's no
notion of a "next address").
- f_reqs_on_bus tracks the number of requests currently outstanding
on the bus. This is used for the ICache <-> Memory assumptions
above. We have some internal assertions that check this equals the
sum of the "ext" counters minus the sum of the "rvd" counters.
With these assumptions, we can prove:
- Once asserted, valid_o stays high until a transaction is completed
by ready_i or until branch_i is asserted (which cancels the
transaction).
- While the transaction is pending, addr_o remains stable.
- While the transaction is pending, err_o remains stable and, if
err_o is asserted, so does err_plus2_o.
- While the transaction is pending, if err_o and err_plus2_o are
high then bottom 16 bits of the returned instruction data imply an
uncompressed instruction.
- While the transaction is pending, if err_o is low then the bottom
16 bits of the returned instruction remain stable.
- While the transaction is pending, if err_o is low and the bottom
16 bits of the returned instruction imply an uncompressed
instruction then the top 16 bits of the returned instruction
remain stable.
To get this working, you need a corresponding patch in Edalize, which
adds SymbiYosys as an EDA tool.
At the moment, this proves a couple of simple bus assertions. Later
patches will add more.
There are currently some rough edges to this flow:
(1) We use a hacky pre_build hook to run sv2v and edit the files in
the work tree. Among other problems, this means that the any
failure messages that come out of sby have bogus line numbers.
(2) Since we haven't yet got bind support in Yosys, we have to
include a fragment from the design itself.
Verible is still experimental, but having a newer version in CI helps us
to make use of some of its newer features as we move forward (such as
waivers).
This commit contains some final optimizations regarding the bit
manipulation extension as well as the parametrization into a balanced
version and a full performance version.
Balanced Version:
* Supports ZBB, ZBS, ZBF and ZBT extensions
* Dual cycle instructions:
ror[i], rol, cmov, cmix fsl, fsr[i]
* Everything else completes in a single cycle.
Full Version:
* Supports all 32b sub extensions.
* Dual cycle instructions:
ror[i], rol, cmov, cmix fsl, fsr[i], crc32[c], bext, bdep
* Everything else completes in a single cycle.
Notable Changes:
* bext/bdep are now multi-cycle: Sharing additional register
with multiplier module
* grev/gorc instructions are implemented in separate structures
rather than sharing the shifter or butterfly network.
* Speed up decision on using rs1 or rs3 for alu_operand_a by
introducing single-bit register, to identify ternary
instructions in their first cycle.
* Introduce enumerated parameter to chose bit manipulation
implementation
Signed-off-by: ganoam <gnoam@live.com>
- invalidate all ways on a tag error to prevent xprop from the data
error signal and reduce the likelyhood of multi-way allocations
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
Although CSR_SECURESEED is unreadable, an attacker can write a new seed,
which brings convenience to the attack. This patch is used to XOR the
historical seed, so that even if the attacker writes a new value to
CSR_SECURESEED , he cannot know the value of the seed.
Signed-off-by: Xiang Wang <merle@hardenedlinux.org>
