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Author SHA1 Message Date
Philipp Wagner
fa31484a6a Lint: Fix signal width in tracer 
These width warnings are only visible if RVFI is enabled and reported by
Verilator lint.
 2019-09-17 13:29:37 +01:00
Philipp Wagner
cc18a5e7d0 Ignore common editor files in Git 
Also removes the include/riscv_config.sv.bak line, which was added
in 346d14c5. We have no code that generates this file any more.
 2019-09-17 13:15:10 +01:00
udinator
80e231dd8b
Add interrupt testing, and update some debug test checks (#324) 2019-09-16 16:58:28 -07:00
taoliug
369f56bad0 Integrate with the new riscv-dv user extension flow (#323) 2019-09-16 15:06:36 -07:00
udinator
2c71a26680
Update google_riscv-dv to google/riscv-dv@0d2b5b7 (#321) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision 0d2b5b7b8b1cdbce74d9e123a427052b12accd7b

* Add user extension support (google/riscv-dv#163) (taoliug)
* Update README (google/riscv-dv#162) (taoliug)
* Fix compilation issue (google/riscv-dv#161) (taoliug)
* Fix compilation issue (google/riscv-dv#160) (taoliug)
* Adding dsim support (google/riscv-dv#159) (taoliug)
* Fix RV64A typo (google/riscv-dv#158) (taoliug)
 2019-09-16 13:43:35 -07:00
Philipp Wagner
87e50a62a9 ibex_riscv_compliance: Adjust to simutil_verilator 
Now that verilated_toplevel.h always generates the right class we don't
need to call VERILATED_TOPLEVEL() any more.
 2019-09-16 14:53:54 +01:00
Philipp Wagner
7a0614a1d0 simutil_verilator: Always produce toplevel class 
Previously, verilated_toplevel.h contained a macro, VERILATED_TOPLEVEL()
to produce a class TOPLEVEL (whatever the toplevel happens to be). This
required all compilation units referring to that TOPLEVEL class to call
the macro.

After this change, the class is always generated in
verilated_toplevel.h. For that to work, a new define TOPLEVEL_NAME must
be globally set (e.g. passed to the compiler with -DTOPLEVEL_NAME=xxx).
 2019-09-16 14:53:54 +01:00
Greg Chadwick
9958d30063 [DV] Fix latch in simple bus 
Fixes #297
 2019-09-16 13:36:23 +01:00
taoliug
0667c14f15 [DV] Standardize logging, allow parallel simulation (#315) 2019-09-15 12:16:14 -07:00
taoliug
7280301369
Fix ELF section name (#314) 2019-09-13 16:11:41 -07:00
taoliug
54eb5c2456
Fix regression failure (#313) 2019-09-13 16:02:34 -07:00
udinator
3fcf5a634d
Update google_riscv-dv to google/riscv-dv@c98d89c (#312) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision c98d89cdff7b56d9911904e05e6b46e005233280

* Interrupt test integration (Udi)
* Update README for illegal/hint instruction (google/riscv-dv#155)
  (taoliug)
* Refactor illegal/hint instruction generation (google/riscv-dv#154)
  (taoliug)
* Skip x0 in GPR save/restore (google/riscv-dv#153) (taoliug)
* Move user_define.h to the beginning of the program (google/riscv-
  dv#151) (taoliug)
* Add user_define.h (google/riscv-dv#149) (taoliug)
* Move instr_bin to a separate section (google/riscv-dv#148) (taoliug)
* Remove temp files (google/riscv-dv#145) (taoliug)
* Move dv_defines.svh outside the package (google/riscv-dv#144)
  (taoliug)
* Fix typo (google/riscv-dv#141) (taoliug)
* Refactored loop instruction stream, reduce global reserved registers
  (google/riscv-dv#139) (taoliug)
* Remove obsolete sample program (google/riscv-dv#138) (taoliug)
* Update readme (google/riscv-dv#137) (taoliug)
* Skip kernel instruction/data pages when not needed (google/riscv-
  dv#136) (taoliug)
* Re-organize data page generation (google/riscv-dv#135) (taoliug)
* Re-organize text and data section (google/riscv-dv#134) (taoliug)
* Refine the bare program mode (google/riscv-dv#133) (taoliug)
* Add a bare program mode (google/riscv-dv#130) (taoliug)
* Allow running riscv-dv from other directories (google/riscv-dv#128)
  (taoliug)
* Fix trace compare issue (google/riscv-dv#123) (taoliug)
* Optimize for constraint solving performance (google/riscv-dv#122)
  (taoliug)
* Avoid ISS simulation timeout (google/riscv-dv#121) (taoliug)
* Optimize irun randomization performance (google/riscv-dv#120)
  (taoliug)
* fix ius compile/simulation warnings (Tao Liu)
* Fix ius compilation failure (Tao Liu)
* Fix google/riscv-dv#109 ius constraint solver failure (Tao Liu)
* Add ebreak sequence generation and cmdline options (Udi)
* Added dret instruction to random generation (Udi)
* Tighten up regex in spike log tracer. (Dave Estes)
* Fix generation of debug handshake (Udi)
* Fix wfi generation, add indent to core_initialization handshake
  (Udi)
 2019-09-13 14:34:56 -07:00
Tom Roberts
f025236a22 [I-side] - Fix issues found in tracing example 
- Fixes #288
- Add missing grant qualification to stop incorrect address updates
- Make RTL robust to spurious rvalid signalling
- Make sure a request is held until granted
- Remove incorrect assertion
 2019-09-12 08:47:09 +01:00
Philipp Wagner
6b03bc6326 Run clang-format on all source files 2019-09-11 12:00:49 +01:00
Philipp Wagner
6afc7eae16 Add lowRISC standard clang-format file 
We use the Google C++ coding style
(https://google.github.io/styleguide/cppguide.html) with some
clarifications to make it more applicable for C, inspired by BoringSSL
(https://boringssl.googlesource.com/boringssl/+/HEAD/STYLE.md).
 2019-09-11 12:00:49 +01:00
Pirmin Vogel
85ae06d054 Controller: fix nmi_mode default assignment 
Without this commit, the `nmi_mode` register is continuously cleared and
set again, and the core can never handle the NMI.

This resolves lowRISC/ibex#300 reported by @udinator.
 2019-09-11 10:45:26 +01:00
udinator
ac22439374
Update slave_driver grant timing to pass Ibex assertion checks (#295) 2019-09-09 14:31:29 -07:00
Pirmin Vogel
8d3d87ae53 Controller: Fix exception cause ID of fast interrupts 
This commit fixes the generation of the exception cause ID for fast
interrupts. Without this commit, the core tries to handle fast
interrupts using the handlers of other interrupts like external,
software, and timer interrupts.

This commit resolves lowRISC/ibex#290 reported by @udinator.
 2019-09-09 13:05:48 +01:00
Tom Roberts
b87ed7c82e [I-side] - Fix assertion error 
- Assertion was added in the wrong file
 2019-09-09 09:06:31 +01:00
pbing
e2110e2a46 Instruction set extensions M and C may be swapped 2019-09-07 17:54:26 +01:00
Udi
7ddee54f9f Fix syntax error 2019-09-07 10:24:27 +01:00
Rahul Behl
60de915d6b Adding Compressed Instruction support in tracer 
Added compressed instruction decoder in the tracer to correctly
trace compressed instructions with their mnemonics. Fixes #197
 2019-09-06 15:43:53 +01:00
Pirmin Vogel
1162b995fa CSRs: reset dcsr.XDEBUGVER to XDEBUGVER_STD instead of 0 
This field is read only and should be set to the right value straight
away.

This fixes lowRISC/ibex#285.
 2019-09-06 15:32:15 +01:00
Tom Roberts
16177fe8db [RTL] Fix I-side timing loop 
- See issue #265 (partially fixes)
- Remove path from instr_rvalid_i to instr_req_o
- Prefetch buffer unit can now issue up to two outstanding requests
- Structure moved from state machine to request queue
- Change fetch fifo to use an unaligned flag rather than updating
  the address each time
 2019-09-06 09:24:57 +01:00
Greg Chadwick
bec84ca2b1 Add core_sleep_o to ibex interface 
Signals the core is totally idle (WFI with no outstanding memory
transactions).  Fixes #258
 2019-09-06 08:44:48 +01:00
Tom Roberts
36db104160 [RTL] - Remove timing loop in LSU 
- Relates to issue #265
- External signals data_rvalid_i and data_err_i were factored
  into the external data_req_o signal
- To improve timing, these signals are decoupled
- The second part of an unaligned transaction will now be issued
  even if the first received an error response
- The state machine will service the abandoned requests
- pmp_err_q fixed to only update at specific times
 2019-09-05 08:35:54 +01:00
udinator
e9c2b2ecb3
Added dret and ebreak tests (#281) 2019-09-04 16:14:41 -07:00
Greg Chadwick
d14312c3cc Replace cluster_id/core_id with hart_id (#29) 
If you're migrating from the previous interface you can use

logic [31:0] hart_id;
assign hart_id = {21'b0, cluster_id_i[5:0], 1'b0, core_id_i[3:0]};

...

ibex_core #(
  ...
) u_core (
  ...

  // replace core_id_i and cluster_id_i
  .hart_id_i(hart_id),

  ...
);
 2019-09-03 14:18:39 +01:00
Rahul Behl
9b51b1143a CSR: Access checks on Debug CSRs 
- The RISC-V Debug Spec v.0.13.2 (p.41) mandates that the core
    debug CSRs dcsr, dpc, dscratch0 and dscratch1 must not be
    accessible if not in debug mode. Fixes #275
 2019-09-03 12:14:49 +01:00
Tom Roberts
892ad8a621 [RTL] - Add PMP module 
- Instantiate generic PMP module
- Wire up I-side and D-side PMP faults
- The output of the PMP check is used to gate external bus requests from the
  I-side and LSU
- Each of those units progresses with their request as-if it was granted
  externally and registers the PMP error
- The error is then sent to the controller at the appropriate time to trigger
  an exception
 2019-08-29 17:43:37 +01:00
Pirmin Vogel
6ecf83124a Register file: update comments 
This commit updates the comments inside the latch-based register file.
Some of them were outdated or just wrong.
 2019-08-29 15:24:18 +01:00
Pirmin Vogel
d79722ba47 Controller: change behavior of DRET instruction 
Executing a DRET instruction outside of debug mode now causes an
illegal instruction exception as mandated by the Debug Spec v0.13.2
p.41.

This resolves lowRISC/ibex#270.
 2019-08-29 11:59:04 +01:00
udinator
68b170638a
Update interrupt mode, add debug mode WFI test (#268) 2019-08-28 10:00:36 -07:00
Philipp Wagner
2b93475864 Lint: Update Verilator waiver file 
PR #236 broke the Verilator lint since lines changed. Fix that.
 2019-08-27 21:32:28 +01:00
taoliug
6a88d1ed03
Update google_riscv-dv to 102791d (#266) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision 102791dbb7eb992d3bc22336d2e4e5f0d688e761

* Merge pull request #104 from google/flow (taoliug)
* Remove debug print (Tao Liu)
* Merge pull request #103 from google/flow (taoliug)
* Improve randomization performance (Tao Liu)
* Merge pull request #102 from udinator/debug (taoliug)
* Prevent x0 from being used as load adress register (Udi)
 2019-08-27 11:23:31 -07:00
Philipp Wagner
7eee24c094 Mention CREDITS.md in license header 2019-08-27 18:10:02 +01:00
Philipp Wagner
14b8f88957 Replace author credits in files with CREDITS.md 
We currently have a documentation block at the beginning of each file,
containing author credits and module-level documentation. The
module-level documentation is retained for historic reasons and
duplicated with the newer comments below it.

For the authors, maintaining author credits in the file is error-prone,
as this information gets outdated very soon. A more reliable way to see
who modified a file is to use the history information in git.
Additionally, we now have the CREDITS.md file, which lists all
contributors, even the ones which don't appear in the git history (e.g.
because the code was copied and commited by someone else).
 2019-08-27 18:10:02 +01:00
Philipp Wagner
c98ab65df2 Add link to CREDITS.md from README.md 2019-08-27 18:10:02 +01:00
Philipp Wagner
1cf11dcf8c Add CREDITS.md file 
This file lists all code contributors to Ibex as of today, and
acknowledges the great work done by the PULP team at ETH Zürich.

The names in this file have been compiled from the git history, and all
authors which are named in the individual source files.
 2019-08-27 18:10:02 +01:00
udinator
2421472395
Integrate risc-v stream generator handshake into Ibex sim flow (#264) 2019-08-26 15:18:30 -07:00
udinator
ce8be4f2fd
Update google_riscv-dv to google/riscv-dv@faddfa4 (#263) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision faddfa49f456f3f8ef8c4231865994b7b13aa96d

* Obsolete test clean up (Tao Liu)
* Remove the old flow (Tao Liu)
* minor fix, update README for A extension support (Tao Liu)
* Add basic atomic instruction test (Tao Liu)
* Add RV32A/RV64A instructions (google/riscv-dv#95) (Tao Liu)
* Fix the missing GPR save operations for exception handling (Tao Liu)
* Generate handshake sequence to communicate with testbench (Udi)
* Fix compare error (Tao Liu)
* Fix compare error (Tao Liu)
* Initial signature enum for handshake protocol (Udi)
 2019-08-26 11:41:37 -07:00
Felix Yan
5d1f8e16bc Correct a typo in doc/verification.rst 2019-08-23 09:02:06 +01:00
Philipp Wagner
399f0b7e77 Update documentation how to run riscv-compliance 
Upstream has now included ibex support, we don't need to use a custom
fork any more. Update the documentation for that.

Fixes #214
 2019-08-22 23:27:13 +01:00
Philipp Wagner
cfb6fc4963 CI: Run the compliance tests for all ISA variants 
rv32imc doesn't include all i and m tests, we need to call the test
suite on these extensions separately.
 2019-08-22 23:27:13 +01:00
taoliug
e2b9c17c0b
Update google_riscv-dv to e81acc9 (#257) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision e81acc9ab4f692ff205a207c2dc3d9f2b0284d39

* Merge pull request #89 from google/dev (taoliug)
* Fix mtvec alignement (Tao Liu)
 2019-08-21 18:22:58 -07:00
taoliug
03df591266
Make mtvec writable, remove previous workaround (#256) 2019-08-21 18:16:51 -07:00
taoliug
2601e8d898
Test cleanup (#255) 2019-08-21 17:19:16 -07:00
taoliug
a752277247
Update google_riscv-dv to 73274f2 (#254) 
Update code from upstream repository https://github.com/google/riscv-
dv to revision 73274f227000f1316cb201a8503aad437e427948

* Merge pull request #88 from google/dev (taoliug)
* Fix spike log processing issue (Tao Liu)
* Merge pull request #87 from google/dev (udinator)
* Add vectored interrupt support (Tao Liu)
* Merge pull request #85 from udinator/debug (udinator)
* Add debug sub-programs, and extra options to generator (Udi)
* Merge pull request #84 from imphil/fix-apache-urls (taoliug)
* Fix license URLs in comments (Philipp Wagner)
 2019-08-21 17:14:15 -07:00
udinator
9311b25fdb
Consolidate some debug generation options, and make the signature_addr handshake optional (#253) 2019-08-21 11:00:17 -07:00
udinator
3bc83365ef
Add more debug tests (#251) 2019-08-20 11:03:15 -07:00