Greg Chadwick a646737d4d [rtl] Cannot add M mode executable PMP regions when MML = 1 ... A rule that allows M mode execution (either M mode only or shared M/U mode) cannot be added when MML is set, unless RLB is also set. Fixes #1740		2022-08-18 15:45:27 +01:00
..
ibex_alu.sv	[lint] Minor fixes	2022-04-12 08:38:35 -07:00
ibex_branch_predict.sv	Fix Xcelium warnings	2020-11-18 10:16:48 +00:00
ibex_compressed_decoder.sv	[style] Indent module header with two spaces	2021-08-31 15:30:28 +02:00
ibex_controller.sv	Fix incorrect debug_cause priority against riscv-debug 1.0.0-STABLE	2022-08-05 12:03:36 +01:00
ibex_core.f	Merge pull request #624 from ganoam/fpga-opt-perf-mon-pr	2020-03-06 12:49:51 +01:00
ibex_core.sv	[rtl, icache] Rework invalidation logic	2022-08-11 09:21:51 +01:00
ibex_counter.sv	[rtl] Fix retired instruction counters	2021-09-17 12:28:10 +01:00
ibex_cs_registers.sv	[rtl] Cannot add M mode executable PMP regions when MML = 1	2022-08-18 15:45:27 +01:00
ibex_csr.sv	[style] Indent module header with two spaces	2021-08-31 15:30:28 +02:00
ibex_decoder.sv	[rtl] Remove redundant comments in decoder	2021-12-16 14:18:00 +01:00
ibex_dummy_instr.sv	[rtl] Add SEC_CM markers for security features	2022-03-09 08:57:24 +00:00
ibex_ex_block.sv	[style] Indent module header with two spaces	2021-08-31 15:30:28 +02:00
ibex_fetch_fifo.sv	Move NT branch addr calculation to ID stage	2021-11-18 13:05:19 +00:00
ibex_icache.sv	[rtl, icache] Rework invalidation logic	2022-08-11 09:21:51 +01:00
ibex_id_stage.sv	[rtl] Flush controller in PMP CSR write ops	2022-08-05 15:50:42 +03:00
ibex_if_stage.sv	[rtl, icache] Rework invalidation logic	2022-08-11 09:21:51 +01:00
ibex_load_store_unit.sv	[dv,fcov] Implement Misaligned Mem Error coverage	2022-07-21 01:02:15 +03:00
ibex_lockstep.sv	[rtl, icache] Rework invalidation logic	2022-08-11 09:21:51 +01:00
ibex_multdiv_fast.sv	[rtl] Add SEC_CM markers for security features	2022-03-09 08:57:24 +00:00
ibex_multdiv_slow.sv	[rtl] Add SEC_CM markers for security features	2022-03-09 08:57:24 +00:00
ibex_pkg.sv	Update crash dump to contain mtval	2022-06-16 07:58:19 -07:00
ibex_pmp.sv	[lint] Minor fixes	2022-08-05 12:25:36 -07:00
ibex_pmp_reset_default.svh	[rtl,doc] Add customisable PMP reset values	2022-01-24 10:01:36 +00:00
ibex_prefetch_buffer.sv	[rtl] Remove "mispredict" ports from prefetch buffer	2022-04-04 16:56:04 +01:00
ibex_register_file_ff.sv	[regfile] Add countermeasure label	2022-04-13 14:36:52 -07:00
ibex_register_file_fpga.sv	[regfile] Add countermeasure label	2022-04-13 14:36:52 -07:00
ibex_register_file_latch.sv	[regfile] Add countermeasure label	2022-04-13 14:36:52 -07:00
ibex_top.sv	[rtl] Fix MaxOutstandingDSideAccessesCorrect assertion	2022-08-11 15:44:41 +01:00
ibex_top_tracing.sv	[cosim,dv] Add support to set mcount registers	2022-07-25 08:51:31 +01:00
ibex_tracer.sv	[ibex_tracer] Void cast function calls	2022-01-20 16:59:22 -08:00
ibex_tracer_pkg.sv	[rtl, bitmanip] Add xperm.[nbh] instruction (Zbp, draft v.0.93)	2021-12-06 11:14:49 +01:00
ibex_wb_stage.sv	[rtl] Fix retired instruction counters	2021-09-17 12:28:10 +01:00