Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
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2015-11-27 11:25:28 +01:00
docs/datasheet Add a basic datasheet for RI5CY 2015-09-09 18:35:07 +02:00
include Fix instruction tracing, removed collision between custom* and our opcodes 2015-11-27 10:54:37 +01:00
.gitignore Added vim swap file 2015-07-24 15:26:32 +02:00
alu.sv Remove some spaces 2015-10-30 13:50:16 +01:00
compressed_decoder.sv Update compressed decoder to RVC 1.9 2015-10-27 12:39:59 +01:00
controller.sv Make sure there are no two branches that are taken back-to-back 2015-11-23 16:41:57 +01:00
cs_registers.sv Fix a bug in the PCER CSR registers, it was not possible to activate more than the basic performance counter 2015-11-18 17:22:07 +01:00
debug_unit.sv This should fix most of the debug features 2015-11-19 14:17:07 +01:00
decoder.sv Merge remote-tracking branch 'origin/master' into exc_ctrl 2015-11-17 10:36:15 +01:00
ex_stage.sv Make sure branches are only done once 2015-11-23 16:51:06 +01:00
exc_controller.sv This should fix most of the debug features 2015-11-19 14:17:07 +01:00
hwloop_controller.sv Fixed issue that hardware loops with same endpoint did not work 2015-11-27 11:25:28 +01:00
hwloop_regs.sv Fixed issue that hardware loops with same endpoint did not work 2015-11-27 11:25:28 +01:00
id_stage.sv This should fix most of the debug features 2015-11-19 14:17:07 +01:00
if_stage.sv Remove branch_req_Q signal, no need for it anymore :-) 2015-11-23 16:53:49 +01:00
load_store_unit.sv Add error signals to LSU 2015-10-19 19:43:58 +02:00
mult.sv Merge branch 'remove_vect' 2015-10-18 19:57:42 +02:00
prefetch_buffer.sv Prefix all modules with riscv_ to avoid future conflicts 2015-10-06 12:18:41 +02:00
prefetch_L0_buffer.sv Prefix all modules with riscv_ to avoid future conflicts 2015-10-06 12:18:41 +02:00
register_file.sv Add test_en to register file clock gates 2015-10-28 12:47:33 +01:00
riscv_core.sv Fix instruction tracing, removed collision between custom* and our opcodes 2015-11-27 10:54:37 +01:00