Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
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Sven Stucki 5ede08fc29 Remove instr_core_if and rewire I$ directly to IF stage
This is a preliminary step for the new IF. The IF has not yet been updated -
the core won't work like this (work-in-progress!).
2015-08-25 15:34:44 +02:00
include Cleanup defines 2015-08-03 15:01:03 +02:00
.gitignore Added vim swap file 2015-07-24 15:26:32 +02:00
alu.sv Updated all file headers 2015-07-24 15:26:12 +02:00
compressed_decoder.sv Four more compressed instructions 2015-07-24 18:24:18 +02:00
controller.sv Remove dead signals 2015-08-17 15:19:48 +02:00
cs_registers.sv Move debug from CS registers to debug unit as they do not need to be 2015-08-14 16:31:03 +02:00
debug_unit.sv Move debug from CS registers to debug unit as they do not need to be 2015-08-14 16:31:03 +02:00
ex_stage.sv Remove dead signals 2015-08-17 15:19:48 +02:00
exc_controller.sv Updated all file headers 2015-07-24 15:26:12 +02:00
id_stage.sv Remove dead signals 2015-08-17 15:19:48 +02:00
if_stage.sv Remove instr_core_if and rewire I$ directly to IF stage 2015-08-25 15:34:44 +02:00
instr_core_interface.sv Updated all file headers 2015-07-24 15:26:12 +02:00
load_store_unit.sv Updated all file headers 2015-07-24 15:26:12 +02:00
mult.sv Updated all file headers 2015-07-24 15:26:12 +02:00
register_file.sv Updated all file headers 2015-07-24 15:26:12 +02:00
riscv_core.sv Remove instr_core_if and rewire I$ directly to IF stage 2015-08-25 15:34:44 +02:00
wb_stage.sv Remove dead signals 2015-08-17 15:19:48 +02:00