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Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
c6eeb34f57
Convert the documentation to restructured text. It looks slightly
different to the previous Word document, but can better be handled by
source control. It also automatically handles the versioning.
To build it:
python -m venv venv
source venv/bin/activate
pip install -r requirements.txt
make html
make latexpdf
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| ci | ||
| doc | ||
| include | ||
| .gitignore | ||
| .gitlab-ci.yml | ||
| LICENSE | ||
| README.md | ||
| src_files.yml | ||
| zeroriscy_alu.sv | ||
| zeroriscy_compressed_decoder.sv | ||
| zeroriscy_controller.sv | ||
| zeroriscy_core.sv | ||
| zeroriscy_cs_registers.sv | ||
| zeroriscy_debug_unit.sv | ||
| zeroriscy_decoder.sv | ||
| zeroriscy_ex_block.sv | ||
| zeroriscy_fetch_fifo.sv | ||
| zeroriscy_id_stage.sv | ||
| zeroriscy_if_stage.sv | ||
| zeroriscy_int_controller.sv | ||
| zeroriscy_load_store_unit.sv | ||
| zeroriscy_multdiv_fast.sv | ||
| zeroriscy_multdiv_slow.sv | ||
| zeroriscy_prefetch_buffer.sv | ||
| zeroriscy_register_file.sv | ||
| zeroriscy_register_file_ff.sv | ||
| zeroriscy_tracer.sv | ||
zero-riscy: RISC-V Core
zero-riscy* is a small 2-stage RISC-V core derived from RI5CY.
zero-riscy fully implements the RV32IMC instruction set and a minimal set of RISCV privileged specifications. zero-riscy can be configured to be very small by disabling the RV32M extensions and by activating the RV32E extensios. This configuration is called micro-riscy
The core was developed as part of the PULP platform for energy-efficient computing and is currently used as the control core for PULP and PULPino.
Documentation
A datasheet that explains the most important features of the core can be found in the doc folder.