Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

cpucorehardwarerisc-vrv32

Sven Stucki de0d3dc76d Small cosmetics on IF stage		2015-08-28 15:41:58 +02:00
include	Fix jalr stall and make jump more efficient	2015-08-27 13:57:13 +02:00
.gitignore	Added vim swap file	2015-07-24 15:26:32 +02:00
alu.sv	Updated all file headers	2015-07-24 15:26:12 +02:00
compressed_decoder.sv	Added missing compressed instruction: c.slt	2015-08-27 09:39:22 +02:00
controller.sv	Add performance counters	2015-08-28 09:57:37 +02:00
cs_registers.sv	Take #3, don't mix blocking and non-blocking assignments	2015-08-28 14:01:39 +02:00
debug_unit.sv	Move debug from CS registers to debug unit as they do not need to be	2015-08-14 16:31:03 +02:00
ex_stage.sv	Remove dead signals	2015-08-17 15:19:48 +02:00
exc_controller.sv	Silence exception warning	2015-08-28 11:31:09 +02:00
id_stage.sv	Add performance counters	2015-08-28 09:57:37 +02:00
if_stage.sv	Small cosmetics on IF stage	2015-08-28 15:41:58 +02:00
instr_core_interface.sv	Optimized IF intermediate step	2015-08-25 15:36:28 +02:00
load_store_unit.sv	Updated all file headers	2015-07-24 15:26:12 +02:00
mult.sv	Updated all file headers	2015-07-24 15:26:12 +02:00
register_file.sv	Updated all file headers	2015-07-24 15:26:12 +02:00
riscv_core.sv	Fix external performance counters	2015-08-28 13:43:23 +02:00
wb_stage.sv	Remove dead signals	2015-08-17 15:19:48 +02:00