Rupert Swarbrick fe84d64d79 [verilator] Slight refactor in ibex_tracer to avoid BLKSEQ warning ... The existing code wanted to open file_handle as a trace file if necessary and then use it on that clock cycle. So it (sensibly) used a blocking assignment. Verilator now warns about blocking assignments to globals in "sequential logic processes" (the always_ff that is driving everything). This is sort of easy to fix: just use an "always" block! This commit looks slightly more involved because I've changed things to pass the file handle to printbuffer_dumpline as an argument. It makes the state update (where we open the file handle) a little easier to follow.		2023-11-22 09:46:03 +00:00
..
ibex_alu.sv	[lint] Minor fixes	2022-04-12 08:38:35 -07:00
ibex_branch_predict.sv	Fix Xcelium warnings	2020-11-18 10:16:48 +00:00
ibex_compressed_decoder.sv	[style] Indent module header with two spaces	2021-08-31 15:30:28 +02:00
ibex_controller.sv	Avoid explicit module names references to signals	2023-03-10 14:47:17 +00:00
ibex_core.f	Merge pull request #624 from ganoam/fpga-opt-perf-mon-pr	2020-03-06 12:49:51 +01:00
ibex_core.sv	[dv] Improve interrupt signalling to cosim	2023-04-27 12:04:22 +00:00
ibex_counter.sv	[rtl] Fix retired instruction counters	2021-09-17 12:28:10 +01:00
ibex_cs_registers.sv	[rtl] Fix MISA X bit for balanced bitmanip config	2023-03-02 10:15:34 +00:00
ibex_csr.sv	[style] Indent module header with two spaces	2021-08-31 15:30:28 +02:00
ibex_decoder.sv	[rtl] Remove redundant comments in decoder	2021-12-16 14:18:00 +01:00
ibex_dummy_instr.sv	[rtl] Add SEC_CM markers for security features	2022-03-09 08:57:24 +00:00
ibex_ex_block.sv	[style] Indent module header with two spaces	2021-08-31 15:30:28 +02:00
ibex_fetch_fifo.sv	Move NT branch addr calculation to ID stage	2021-11-18 13:05:19 +00:00
ibex_icache.sv	[lint] Make case statements unique case	2022-08-24 15:33:38 -07:00
ibex_id_stage.sv	Remove TODOs	2023-04-25 14:23:34 +00:00
ibex_if_stage.sv	[rtl] Add missing `include to ibex_if_stage	2023-04-11 14:22:05 +00:00
ibex_load_store_unit.sv	[dv] Various fcov fixes and tweaks	2022-11-16 12:52:33 +00:00
ibex_lockstep.sv	[dv] Improve interrupt signalling to cosim	2023-04-27 12:04:22 +00:00
ibex_multdiv_fast.sv	[rtl] Add SEC_CM markers for security features	2022-03-09 08:57:24 +00:00
ibex_multdiv_slow.sv	[rtl] Add SEC_CM markers for security features	2022-03-09 08:57:24 +00:00
ibex_pkg.sv	[rtl] Protect core_busy_o with a multi-bit encoding	2022-10-25 12:52:01 +02:00
ibex_pmp.sv	[ibex_pmp/lint] Declare functions before using them	2023-10-19 07:58:30 +00:00
ibex_pmp_reset_default.svh	[rtl,doc] Add customisable PMP reset values	2022-01-24 10:01:36 +00:00
ibex_prefetch_buffer.sv	[rtl] Remove "mispredict" ports from prefetch buffer	2022-04-04 16:56:04 +01:00
ibex_register_file_ff.sv	[rtl] Fix dummy instructions	2022-10-31 17:42:12 +00:00
ibex_register_file_fpga.sv	[rtl] Fix dummy instructions	2022-10-31 17:42:12 +00:00
ibex_register_file_latch.sv	[rtl] Fix dummy instructions	2022-10-31 17:42:12 +00:00
ibex_top.sv	[dv] Add asserts to check alerts for memory integrity failures	2023-05-15 13:51:06 +00:00
ibex_top_tracing.sv	[dv] Improve interrupt signalling to cosim	2023-04-27 12:04:22 +00:00
ibex_tracer.sv	[verilator] Slight refactor in ibex_tracer to avoid BLKSEQ warning	2023-11-22 09:46:03 +00:00
ibex_tracer_pkg.sv	[rtl, bitmanip] Add xperm.[nbh] instruction (Zbp, draft v.0.93)	2021-12-06 11:14:49 +01:00
ibex_wb_stage.sv	[rtl] Improve FI hardening around data_rvalid_i	2023-01-16 18:53:17 +01:00