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Author SHA1 Message Date
stnolting
fa544d1fe3 [cpu] fix minor bug in instruction request bus 
The privilege level was hardwired so it always showed "user-mode".
 2024-02-03 21:21:09 +01:00
stnolting
9600c33550 ✨ add MMU module 2024-02-03 20:57:25 +01:00
stnolting
20139e3626 [cpu] integrate MMU module 2024-02-03 20:57:09 +01:00
stnolting
56e423d466 [lib] add MMU HAL 2024-02-03 20:56:53 +01:00
stnolting
39a436db7b [top] fix JTAG reset default value 
input is low-active, so the default is high
 2024-02-03 11:16:04 +01:00
stnolting
b12f202b59 [docs] add note about trapping when accessing unimplemented CSRs 2024-02-03 11:14:19 +01:00
stnolting
83c0a87f41
Add support for page fault exceptions (#786) 2024-02-03 10:42:07 +01:00
stnolting
bca70566a2 [cpu] add page fault trigger stubs 2024-02-03 08:44:11 +01:00
stnolting
81c9bff863 [control] minor edits 2024-02-03 08:43:49 +01:00
Mikael Mortensen
97072fc350
First update to fix fflags not set correctly 
Signed-off-by: Mikael Mortensen <119539842+mikaelsky@users.noreply.github.com>
 2024-02-02 07:58:32 -08:00
stnolting
243bcef6f1 [rtl] clean-up control unit's entity 2024-02-01 20:29:28 +01:00
stnolting
7dbee1d324 [docs] update CPU trap table 
add page fault exceptions
 2024-02-01 20:14:51 +01:00
stnolting
ca724c74a4 [changelog] add v1.9.4.2 2024-02-01 20:14:25 +01:00
stnolting
d4d857cdf7 [RTE] add page fault support 2024-02-01 20:00:41 +01:00
stnolting
1513d19f38 [RTE] add page fault rap IDs 2024-02-01 20:00:06 +01:00
stnolting
41b3956442 [sw/lib] add page fault mcause codes 2024-02-01 19:59:17 +01:00
stnolting
1e2d9af772 [cpu] add page fault exception trigger 
yet unused, hardwired to zero
 2024-02-01 19:58:33 +01:00
stnolting
badd507128 [control] add page fault exceptions 2024-02-01 19:58:09 +01:00
stnolting
07be39f157 [package] add page fault exceptions 2024-02-01 19:56:49 +01:00
stnolting
2162a1094e
fix trap priority (#784) 2024-01-31 22:13:27 +01:00
stnolting
049f51ab70 [RTE] minor edit 
no info output if UART0 not implemented
 2024-01-31 21:57:50 +01:00
stnolting
3b58dbe16e [changelog] add v1.9.4.1 2024-01-31 21:57:29 +01:00
stnolting
e0f7874749 [RTE] minor edits and cleanups 2024-01-31 21:53:14 +01:00
stnolting
fe29a3b100 [docs] fix trap priority 2024-01-31 21:52:47 +01:00
stnolting
3ad59d4f6a [control] fix trap priority 
instruction_access_fault before instruction_address_misaligned
 2024-01-31 21:52:30 +01:00
stnolting
47859bf634 [control] minor code cleanups 2024-01-31 21:51:45 +01:00
stnolting
6269bd2fcd 🚀 preparing release v1.9.4 2024-01-31 20:46:03 +01:00
stnolting
e3dde60624
Fix for issue #782 (#783) 2024-01-31 17:59:16 +01:00
stnolting
036c578183 update version to v1.9.3.10 2024-01-31 17:52:10 +01:00
Mikael Mortensen
7222b78e35
Fix for issue #782 
Added a illegal instruction exception to the register to register branch of the compressed instruction decoder.

Signed-off-by: Mikael Mortensen <119539842+mikaelsky@users.noreply.github.com>
 2024-01-31 08:09:17 -08:00
stnolting
8e5223485d
🧪 extend switchable clock domain (#780) 2024-01-29 21:55:29 +01:00
stnolting
2d469c6e9c [CHANGELOG] add v1.9.3.9 2024-01-29 21:06:09 +01:00
stnolting
25a5724e35 [docs] extend clock gating section 2024-01-29 21:05:53 +01:00
stnolting
78a1ca1635 extend switchable clock domain 
When the CPU is in sleep mode and clock gating is enabled the CPU itself is shut down together with the CPU's bus switch and - if implemented - the caches.
 2024-01-29 21:00:45 +01:00
stnolting
1e5811e22c
set top entiy input defaults to 'L' or 'H' (#779) 2024-01-29 19:36:45 +01:00
stnolting
8d40d35405 [changelog] add v1.9.3.8 2024-01-29 18:08:03 +01:00
stnolting
3b49056ae1 set top entiy input defaults to 'L' or 'H' 
modeling a pull-down / pull-up "resistor" in case these signals are not explicitly assigned during instantiation
 2024-01-29 17:58:38 +01:00
stnolting
8c2a5ed0ec [processor_check] update run script 
add additional ISA extensions - except C
 2024-01-28 20:38:16 +01:00
stnolting
0f14da2e7e [changelog] typo fix 2024-01-28 20:37:14 +01:00
stnolting
9e5382b7f5 cleanups global .gitignore 2024-01-28 20:36:53 +01:00
stnolting
e8a97c9dc0 cleanup VHDL license headers 2024-01-28 20:36:18 +01:00
stnolting
c95e03978c
Updated FIFO NULL assertion fix (#778) 2024-01-28 19:47:33 +01:00
stnolting
5404d30544 update version to v1.9.3.7 2024-01-28 19:39:19 +01:00
stnolting
8d3078d63c [fifo] minor comment edits 2024-01-28 19:38:45 +01:00
Mikael Mortensen
c5cd9e7c93
Merge pull request #2 from mikaelsky/mikaelsky-patch-2 
NULL assertion fix in FIFO, was PR #766
 2024-01-28 10:29:09 -08:00
Mikael Mortensen
1376f33cb1
NULL assertion fix in FIFO 
Added condition check on fifo_dept_c to ensure we don't get NULL assertions when fifo_depth_c == 1.
Reset function already added.

Signed-off-by: Mikael Mortensen <119539842+mikaelsky@users.noreply.github.com>
 2024-01-28 06:46:45 -08:00
stnolting
4b46f13762
[rtl] improve CPU front end (#777) 2024-01-27 19:42:15 +01:00
stnolting
36a88e820b [changelog] add v1.9.3.6 2024-01-27 19:21:49 +01:00
stnolting
f8ff660309 [rtl] improve front end 
less wait cycles after branches
 2024-01-27 19:11:05 +01:00
stnolting
34c712acbb
🐛 fix typo that renders the clock gating useless (#776) 2024-01-27 18:07:33 +01:00