neorv32

mirror of https://github.com/stnolting/neorv32.git synced 2025-04-20 04:10:40 -04:00

Author	SHA1	Message	Date
stnolting	ff24baf41d	🚀 preparing release v1.10.7 Some checks failed Documentation / SW Framework (push) Has been cancelled Details Documentation / Datasheet (push) Has been cancelled Details Processor / processor simulation (push) Has been cancelled Details Documentation / Deploy to Releases and Pages (push) Has been cancelled Details	2024-12-10 20:57:04 +01:00
stnolting	6f5e1e7c9f	[docs] Fix missing " in makefile (#1117 )	2024-12-10 19:08:51 +01:00
stnolting	28c00aa39f	[.github] use ubuntu 22.04	2024-12-10 18:57:18 +01:00
Lukas Pajak	293c589966	[docs] Fix missing " in makefile	2024-12-10 16:12:35 +01:00
stnolting	4bc8809ea9	[sim] only analyze files from 'rtl' and 'sim' folders #1096	2024-12-08 11:23:04 +01:00
stnolting	a0f43490eb	use vhdl 2008 standard in ghdl simulations (#1096 ) Some checks failed Documentation / SW Framework (push) Has been cancelled Details Documentation / Datasheet (push) Has been cancelled Details Processor / processor simulation (push) Has been cancelled Details Documentation / Deploy to Releases and Pages (push) Has been cancelled Details	2024-12-03 22:13:17 +01:00
stnolting	248296efe7	Merge branch 'main' into main	2024-12-03 21:57:13 +01:00
stnolting	40fae955fc	✨ add ONEWIRE command FIFO; 🐛 fix ONEWIRE status flag (#1113 )	2024-12-03 21:56:46 +01:00
stnolting	29145bba65	Merge branch 'main' into main	2024-12-03 21:42:58 +01:00
stnolting	f9290008ec	Merge branch 'main' into onewire_update_fix	2024-12-03 21:37:32 +01:00
stnolting	66a702d403	[sw] Add UART disable tag (#1112 )	2024-12-03 21:37:11 +01:00
stnolting	9e48921704	[sw/lib] uart: add trailing new line	2024-12-03 19:44:55 +01:00
stnolting	4525d7dbd0	[docs] update onewire section	2024-12-03 19:28:26 +01:00
stnolting	d6c74c7b0a	[changelog] add v1.10.6.9	2024-12-03 19:27:51 +01:00
stnolting	3fc5745ca2	[processor_check] adjust ONEWIRE test code	2024-12-03 19:15:21 +01:00
stnolting	8da24440c6	[rtl] update ONEWIRE module 🐛 fixing a regressions: busy signal was stuck at zero	2024-12-03 19:14:51 +01:00
Lukas Pajak	154642d964	[docs] Add UART_DISABLED and lto to mk example	2024-12-03 11:18:04 +01:00
Lukas Pajak	d4e4469ff7	[sw] Add UART_DISABLED flag to reduce footprint	2024-12-03 10:57:20 +01:00
stnolting	d307bf5fa1	[sw] update onewire HAL	2024-12-01 22:29:54 +01:00
stnolting	38fd3b7f9b	[svd] update onewire registers and bits	2024-12-01 22:29:26 +01:00
stnolting	30153f949b	[sw] update onewire example program	2024-12-01 21:59:16 +01:00
stnolting	99f9331ffd	[top] add onewire fifo generic	2024-12-01 21:58:28 +01:00
stnolting	7992c9f6ff	[TWI] add bus sensing logic (#1111 ) Some checks failed Documentation / SW Framework (push) Has been cancelled Details Documentation / Datasheet (push) Has been cancelled Details Processor / processor simulation (push) Has been cancelled Details Documentation / Deploy to Releases and Pages (push) Has been cancelled Details	2024-12-01 21:20:04 +01:00
stnolting	917ce42bf2	Merge branch 'main' into twi_bus_sensing	2024-12-01 21:08:41 +01:00
stnolting	9521dec61a	[vivado_ip] minor GUI layout edit	2024-12-01 21:02:57 +01:00
stnolting	687c9d38e6	[docs] cleanup doxygen top files	2024-12-01 21:02:22 +01:00
stnolting	6805c849ed	[docs] minor 1-wire image fix	2024-12-01 21:00:58 +01:00
stnolting	2955086dd0	[sw/example] update TWI example program	2024-12-01 20:46:39 +01:00
stnolting	3be222eb79	[changelog] add v1.10.6.8	2024-12-01 20:44:49 +01:00
stnolting	0390a6ef6d	[lib] update TWI HAL	2024-12-01 20:38:24 +01:00
stnolting	12c235860b	[docs] update TWI section	2024-12-01 20:37:36 +01:00
stnolting	8056b357d4	[twi] add bus sensing logic and flags	2024-12-01 20:37:08 +01:00
stnolting	ba4c0037ac	[package] update version ID	2024-12-01 20:34:02 +01:00
stnolting	2e5b1d941e	[sw] Use build folder and add example for more complex project structure (#1107 )	2024-12-01 20:15:14 +01:00
stnolting	0caddcdbae	[docs] add note regarding build artifacts	2024-12-01 19:56:39 +01:00
stnolting	4da94122e0	[common] adjust makefile help menu	2024-12-01 19:56:03 +01:00
stnolting	dcd11fe357	[git] ignore all build directories	2024-12-01 19:34:03 +01:00
Lukas Pajak	8965da8b60	[sw] add build dir as dependency of main.bin	2024-11-28 11:07:40 +01:00
Lukas Pajak	44c4c48ffc	[docs] add hint for more complex projects	2024-11-28 10:53:55 +01:00
Lukas Pajak	e5e9a451fe	[sw] coremark as example for source folder usage	2024-11-28 10:40:52 +01:00
Lukas Pajak	6fe5d36fd3	[sw] use build folder for object files	2024-11-28 10:38:00 +01:00
stnolting	3fe0b11cf5	[rtl] fix some Verilog [sic] issues (#1103 ) Some checks failed Documentation / SW Framework (push) Has been cancelled Details Documentation / Datasheet (push) Has been cancelled Details Processor / processor simulation (push) Has been cancelled Details Documentation / Deploy to Releases and Pages (push) Has been cancelled Details	2024-11-26 20:21:03 +01:00
stnolting	5b9c7664e4	[docs/makefile] Copy figures also for single targets (#1101 )	2024-11-26 20:15:49 +01:00
stnolting	9c2ed5990b	Merge branch 'main' into fixed-docs-makefile	2024-11-26 20:09:29 +01:00
stnolting	041a2dd2a1	[changelog] add v1.10.6.7	2024-11-26 20:00:53 +01:00
stnolting	4d0db3eeff	[dma] signal renaming "config" seems to be a reserved word in Verilog	2024-11-26 19:56:56 +01:00
stnolting	ad1a209f23	🐛 [cache] fix address comparison	2024-11-26 19:56:28 +01:00
stnolting	5a1f6edc7d	[package] update version ID	2024-11-26 19:55:09 +01:00
stnolting	1aea18f617	Fixed typo and cpu_alu architecture renaming for consistency (#1102 )	2024-11-26 19:51:55 +01:00
Lukas Pajak	7a0ac48bce	[docs/makefile] copy images for doxygen and fixes	2024-11-26 14:04:24 +01:00

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7551 commits