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Author SHA1 Message Date
Olof Kindgren
15246e3692 Fix Verilator waiver file 2021-07-05 23:59:19 +02:00
Dave Dribin
57af7204d1 Wire up servant.q output to both LED1 and UART TX 2021-06-28 09:10:04 +02:00
Dave Dribin
c561979c8e Minor update to .pcf 2021-06-28 09:10:04 +02:00
Dave Dribin
0375ba896f Move to board-specific top-level and file set 2021-06-28 09:10:04 +02:00
Dave Dribin
54d5d65b62 Add support for Nandland Go Board 2021-06-28 09:10:04 +02:00
Gwenhael Goavec-Merou
5e74b13c24 Add support for Terasic DE10 Nano Kit 2021-06-22 17:54:50 +02:00
Olof Kindgren
7f7ea07260 Document memory instructions 2021-06-11 21:48:20 +02:00
Olof Kindgren
a1e5a5ea80 Add timing diagram for interrupts and ecall/ebreak 2021-06-10 23:56:10 +02:00
Olof Kindgren
cae472b29e Document one-stage instructions 2021-06-10 18:15:12 +02:00
Olof Kindgren
c4bf02aeb0 Add instruction life cycle flowchart to doc 2021-06-10 16:52:33 +02:00
Olof Kindgren
c2cdd44f73 Expose and document PRE_REGISTER 2021-06-05 22:56:37 +02:00
Sylvain Munaut
259d5a10ed decode: Add option to pre or post register during decoding 
Either the input from instruction bus is registered and the
outputs are generated combinatorially (PRE_REGISTER mode), or
the input from the instruction bus is decoded combinatorially
and the result of decoding is registered (POST_REGISTER mode).

First is smaller because it allows synthesis to optimize decoding
logic with its users, but is slow. The second one is faster but
slightly bigger.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2021-05-28 21:26:54 +02:00
The Gitter Badger
06653f52b2 Add Gitter badge 2021-05-23 18:48:01 +02:00
Olof Kindgren
f373d7bcb6 Reuse immediate regs for RF addresses 2021-05-16 00:09:18 +02:00
Olof Kindgren
14262bfc30 Rewrite logic expression of alu bool operations 2021-05-15 23:07:55 +02:00
Olof Kindgren
1acd829f83 Fix CI after branch renaming 2021-05-05 15:32:02 +02:00
Olof Kindgren
a5c1c8ddc4 Kill off serv_params.vh 2021-04-26 17:04:18 +02:00
Olof Kindgren
c0bb0282a5 Fix up wreq timing diagram 2021-04-26 16:31:56 +02:00
Olof Kindgren
1b6aa66379 Clear t0 in blinky example 2021-04-26 12:59:40 +02:00
Olof Kindgren
1c11365ae8 Simulator-friendly cleanup of misalign_trap_sync 2021-04-22 15:44:18 +02:00
Stefan Wallentowitz
cfb779d3d6 CI Lint with librecores github action linter 
Add the librecores linter, that also does proper annotation to the
source code.
 2021-04-18 23:02:04 +02:00
Olof Kindgren
0519ae4a52 Add verilator waiver file 2021-04-18 23:01:26 +02:00
Olof Kindgren
82c808aa1e Implement byte_valid in a more efficient way 2021-04-18 22:48:55 +02:00
Olof Kindgren
62d5d5f8fb Remove unused wire cnt4 2021-04-18 22:01:32 +02:00
Stefan Wallentowitz
5c303f46b4 Build website automatically and publish to gh-pages 2021-04-18 21:07:27 +02:00
Olof Kindgren
0c601f0872 Fix RF we gating for RF width > 2 2021-04-18 00:13:47 +02:00
Olof Kindgren
4c3ea39b06 Start documenting instruction life cycle 2021-04-18 00:10:10 +02:00
Olof Kindgren
079a5c4250 Remove unused wgo register 2021-04-08 15:36:11 +02:00
Olof Kindgren
9b84539bc0
Add LibreCores badge 2021-03-17 21:14:41 +01:00
Olof Kindgren
548b7fbb41 remove redundant ALU control signal 2021-03-14 23:22:50 +01:00
Olof Kindgren
727bb40a87 Simplify control logic for bool ops 2021-03-14 00:12:29 +01:00
Olof Kindgren
7624466ddd Optimize serv_rf_ram_if 2021-02-15 08:50:24 +01:00
somhi
a6292d46a2 Add support for DECA Max 10 board 2021-02-07 18:20:33 +01:00
somhi
ceddc1876b Sockit notes added 2021-02-07 18:20:33 +01:00
Olof Kindgren
9a0b0e877c Move shifter to mem_if 
This allows reusing the data bus registers for shift amount
 2021-02-06 23:24:23 +01:00
somhi
bc9705bef2 add support for SoCKit development kit board 2021-02-03 22:34:36 +01:00
Olof Kindgren
f70b79fd8f Combine lt and eq regs to cmp_r in serv_alu 2021-02-01 22:37:45 +01:00
Olof Kindgren
308612fd9e Expose WITH_CSR and RESET_STRATEGY in core file 2021-01-26 20:59:49 +01:00
Olof Kindgren
6fbdea58d6 Optimize trap handling 2021-01-23 22:42:26 +01:00
Olof Kindgren
8d5dd77a26 Optimize csr address handling 2021-01-23 22:42:26 +01:00
Olof Kindgren
e8bc87fd0e Add serv_rf_if documentation 2021-01-20 23:48:28 +01:00
Olof Kindgren
e4b773c17b Syntax fixes 2021-01-18 22:47:28 +01:00
Olof Kindgren
5e4181d204 Optimize shift operations 2021-01-18 22:46:51 +01:00
Olof Kindgren
d5febe8f63 Simplify and document trap handling 2021-01-18 22:38:07 +01:00
Olof Kindgren
4a5c5bd588 Update bufreg documentation 2021-01-11 22:09:24 +01:00
Olof Kindgren
17103dd1f5 Merge LSB registers into bufreg 2021-01-11 21:40:45 +01:00
Olof Kindgren
fe6c9b0f83 Optimize bufreg lsb signal and clean up bufreg interface 2021-01-06 22:19:40 +01:00
Olof Kindgren
0bc19ef13c Clean up serv_alu interface 2021-01-06 22:02:13 +01:00
Olof Kindgren
ace7b8ef44 Explain and optimize state counter 2021-01-03 00:01:09 +01:00
Olof Kindgren
25fa6fa83b Clean up and document serv_mem_if 2021-01-02 00:02:23 +01:00