|
serv_bufreg.v
|
Make counter internal in serv_state
|
2020-04-15 10:29:50 +02:00 |
|
serv_csr.v
|
Make counter internal in serv_state
|
2020-04-15 10:29:50 +02:00 |
|
serv_ctrl.v
|
Inline shift_reg
|
2020-05-26 22:43:23 +02:00 |
|
serv_decode.v
|
Declare variables/nets before referenced
|
2020-03-25 23:31:55 +01:00 |
|
serv_mem_if.v
|
Optimize enable signal for mem_if buffers
|
2020-04-15 22:48:28 +02:00 |
|
serv_params.vh
|
Use one-hot encoding for ALU rd sel
|
2019-12-07 23:36:36 +01:00 |
|
serv_rf_if.v
|
Fix lint warnings when CSR is disabled
|
2020-03-25 23:32:12 +01:00 |
|
serv_rf_ram.v
|
Add parameter to disable CSR/interrupts
|
2020-03-02 16:17:26 +01:00 |
|
serv_rf_ram_if.v
|
Add compatibility with Xilinx ISE
|
2020-05-06 20:19:52 +02:00 |
|
serv_rf_top.v
|
Restore nettype to wire in toplevels
|
2020-05-26 22:46:01 +02:00 |
|
serv_state.v
|
Make counter internal in serv_state
|
2020-04-15 10:29:50 +02:00 |
|
serv_top.v
|
Restore nettype to wire in toplevels
|
2020-05-26 22:46:01 +02:00 |
