vortex

mirror of https://github.com/vortexgpgpu/vortex.git synced 2025-04-24 13:57:17 -04:00

Author	SHA1	Message	Date
tinebp	86f20b27dd	SimX multi-ports memory fixes	2024-12-04 21:11:51 -08:00
tinebp	3ace9bbeda	minor updates Some checks are pending CI / setup (push) Waiting to run Details CI / build (32) (push) Blocked by required conditions Details CI / build (64) (push) Blocked by required conditions Details CI / tests (cache, 32) (push) Blocked by required conditions Details CI / tests (cache, 64) (push) Blocked by required conditions Details CI / tests (config1, 32) (push) Blocked by required conditions Details CI / tests (config1, 64) (push) Blocked by required conditions Details CI / tests (config2, 32) (push) Blocked by required conditions Details CI / tests (config2, 64) (push) Blocked by required conditions Details CI / tests (debug, 32) (push) Blocked by required conditions Details CI / tests (debug, 64) (push) Blocked by required conditions Details CI / tests (opencl, 32) (push) Blocked by required conditions Details CI / tests (opencl, 64) (push) Blocked by required conditions Details CI / tests (regression, 32) (push) Blocked by required conditions Details CI / tests (regression, 64) (push) Blocked by required conditions Details CI / tests (scope, 32) (push) Blocked by required conditions Details CI / tests (scope, 64) (push) Blocked by required conditions Details CI / tests (stress, 32) (push) Blocked by required conditions Details CI / tests (stress, 64) (push) Blocked by required conditions Details CI / tests (synthesis, 32) (push) Blocked by required conditions Details CI / tests (synthesis, 64) (push) Blocked by required conditions Details CI / tests (vm, 32) (push) Blocked by required conditions Details CI / tests (vm, 64) (push) Blocked by required conditions Details CI / complete (push) Blocked by required conditions Details	2024-12-04 06:00:19 -08:00
jaewon-lee-github	d1175a03c9	update the code accessing registers in obsoleted way	2024-10-02 14:16:57 -04:00
Jaewon Lee	4a606061d2	Merge branch 'develop' into tensor-core	2024-09-30 16:48:47 -04:00
Blaise Tine	904a6dc136	fixed trace format consistency	2024-07-27 17:24:14 -07:00
Blaise Tine	b3a4d58825	fixed lsu stats	2024-07-23 13:13:51 -07:00
Blaise Tine	eb92e0bdbe	fixed simx lsu-unit bug	2024-07-23 11:29:56 -07:00
Blaise Tine	60f7786e17	BitVector class bug fixes	2024-07-23 09:40:20 -07:00
Blaise Tine	95f59d23a8	simx memory coalescer bug fix	2024-07-23 00:02:43 -07:00
Blaise Tine	a2307a28dc	perf counters update	2024-07-12 19:02:43 -07:00
Nayan Sivakumar Nair	5b0fc8cbd4	Fixes for PR	2024-06-25 03:18:50 -04:00
Nayan Sivakumar Nair	a378aed67c	Moved tc_num, tc_size param to makefile args	2024-06-21 22:23:24 -04:00
Varsha Singhania	99c6a1af5a	Tensor cores in Vortex	2024-06-17 04:28:51 -04:00
Blaise Tine	b3f96e288a	+ support for ZICOND RISC-V extension + RTL decode refactoring	2024-05-20 00:17:24 -07:00
Blaise Tine	717b2e9ba1	enable barrier and spawn skip mode if N=1	2024-05-08 04:23:38 -07:00
Blaise Tine	e84f978502	minor update	2024-05-01 00:02:52 -07:00
Blaise Tine	a167c07e7d	adding wait cycles to wspawn	2024-04-28 04:27:47 -07:00
Blaise Tine	402c911991	simx mem_coalescer	2024-03-24 20:31:36 -07:00
Blaise Tine	d9426d5789	minor update	2024-03-14 21:36:39 -07:00
Blaise Tine	f1522e68f8	simx memory coalescing support	2024-03-14 12:20:39 -07:00
Blaise Tine	840ced22a9	simx refactoring - emulation vs simulation discrete separation	2024-03-12 00:23:42 -07:00

21 commits