tinebp
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22398c991d
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ramulator memory addressing bug fix + platform memory refactoring
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2025-01-26 06:28:51 -08:00 |
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tinebp
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53900bee4f
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bug fixes
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2024-12-26 10:01:36 -08:00 |
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tinebp
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a98d2e24e5
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rtlsim multibanks
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2024-12-16 22:10:57 -08:00 |
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tinebp
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3ace9bbeda
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minor updates
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2024-12-04 06:00:19 -08:00 |
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tinebp
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3b454efd56
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fixes to SimX's multiports memory support
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2024-12-02 17:51:42 -08:00 |
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Blaise Tine
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a9a5ded030
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bitmanip logceil fix
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2024-09-23 23:54:43 -07:00 |
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sij814
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d7e8fd74ff
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source_id = 0
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2024-08-15 19:40:52 -07:00 |
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sij814
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ea34239b43
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changes made for initial feedback
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2024-08-13 16:52:27 -07:00 |
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sij814
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47427ab22e
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regression test with source_id 0
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2024-08-12 16:22:30 -07:00 |
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sij814
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de81baaabf
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hbm for vortex 2.2
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2024-08-12 02:52:47 -07:00 |
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Blaise Tine
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904a6dc136
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fixed trace format consistency
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2024-07-27 17:24:14 -07:00 |
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Blaise Tine
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a5377d78ca
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minor update
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2024-07-21 14:50:59 -07:00 |
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Blaise Tine
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fb141ae522
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Ramulator 2.0 with HBM 2.0 support
Verilator 5.0 support
SimX C++17 requirement
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2024-07-21 06:57:13 -07:00 |
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Blaise Tine
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07c063031f
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tabs cleanup
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2024-03-13 23:19:54 -07:00 |
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Blaise Tine
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ff6f33acff
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simx refactoring: simobject::push(), instr_trace, FUtype, pending_instrs_
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2024-03-11 15:39:49 -07:00 |
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Blaise Tine
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d47cccc157
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Vortex 2.0 changes:
+ Microarchitecture optimizations
+ 64-bit support
+ Xilinx FPGA support
+ LLVM-16 support
+ Refactoring and quality control fixes
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2023-10-19 20:51:22 -07:00 |
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