35 commits

Author	SHA1	Message	Date
Blaise Tine	a06812f93f	minor updates	2022-02-01 22:51:33 -05:00
Blaise Tine	e3e2609f7e	adding unit test for vx_malloc	2022-01-30 05:57:18 -05:00
Blaise Tine	f7887d8720	refactoring device memory allocation and cleanup	2022-01-28 21:57:16 -05:00
Blaise Tine	41d7e6c63a	cummulative fixes, RTL uuid trace, texture unit fixes, simx timing fixes	2021-11-30 07:08:15 -05:00
Blaise Tine	27a65fdee7	driver refactoring	2021-11-14 09:05:15 -05:00
Blaise Tine	9656779d48	minor update	2021-11-14 04:45:06 -05:00
Blaise Tine	1cd833d2c4	minor fixes	2021-10-11 19:02:13 -07:00
Blaise Tine	54bddeee9c	simulation framework refactoring	2021-10-09 10:20:42 -04:00
Blaise Tine	342c07f8d6	minor update	2021-06-28 01:56:09 -04:00
Blaise Tine	76c4909ae9	minor update	2021-06-12 02:22:01 -04:00
Blaise Tine	78a452ea6e	minor update	2021-06-11 12:54:10 -07:00
Blaise Tine	3cc1190cd7	CSRs I/O refactoring	2021-06-11 03:08:07 -07:00
Blaise Tine	2216a3059d	minor update	2021-04-27 05:52:01 -04:00
Blaise Tine	8410c49f53	code refactoring: DRAM => MEM renaming	2021-04-26 00:58:48 -07:00
Blaise Tine	9fda618815	minor typo	2021-02-28 01:58:41 -08:00
Blaise Tine	700f9eea19	moving MUL unit into ALU unit	2021-02-23 13:49:02 -08:00
Blaise Tine	6c1dc96626	simX refactoring + removed oldRTL + CSR updates	2021-02-06 12:52:54 -08:00
Blaise Tine	f18ac24675	afu reset fix	2021-01-12 17:13:47 -08:00
Blaise Tine	b4b5d6f0ab	minor updates	2021-01-12 15:19:38 -08:00
Blaise Tine	7c4823e65c	fixed GPR reset bug, fixed lsu dup loading, fixed riscv-tests	2021-01-11 23:55:09 -08:00
Blaise Tine	abe32ed553	cache optimization - moved read requests to stage1 and eliminating stage3	2020-12-31 07:40:58 -08:00
Blaise Tine	d956e268b9	adding new performance counters (banks utilization and DRAM bus utilization)	2020-12-22 12:33:45 -08:00
Blaise Tine	4bbd7bf408	performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,	2020-12-19 02:45:06 -08:00
Blaise Tine	d5438fd591	merging perf counters	2020-12-08 21:02:39 -08:00
Blaise Tine	2e0f51af80	fixed instr/cycle perf counter	2020-11-12 11:41:25 -08:00
Blaise Tine	112d8ab815	adding CSR support to rtlsim driver	2020-09-04 06:51:31 -04:00
Blaise Tine	e54425404e	fixed driver unrsolved dependencies	2020-08-27 06:41:40 -04:00
Blaise Tine	0b355f228e	ibuffer addition	2020-08-22 00:22:04 -07:00
Blaise Tine	2de61b5982	get device caps from CSRs	2020-06-30 00:08:23 -07:00
Blaise Tine	106d707024	verilator suppor for opae (partial)	2020-06-03 06:22:49 -04:00
Blaise Tine	9e5885b820	adding dram writeenable support + scheduler bug fixes	2020-05-27 19:00:23 -04:00
Blaise Tine	de9fc68ccc	opae fixes	2020-05-06 21:14:53 -07:00
Blaise Tine	a1dc90b951	rtl cache refactory	2020-04-30 17:12:18 -04:00
Blaise Tine	81745f08c9	added config.vh	2020-04-16 07:49:19 -04:00
Blaise Tine	12dc4d6874	refactoring fixes	2020-04-14 19:39:59 -04:00