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3339 commits 27 branches 9 tags 1.6 GiB
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31 commits

Author SHA1 Message Date
MichaelJSr
b2ad2e5281 Added a vpu and vec units 2025-02-09 17:53:09 -08:00
MichaelJSr
a2cfeffcfe Added ifndef statements for the vector extension anywhere they didn't exist already 
Added ifndef statements for the vector extension anywhere they didn't exist already

more ifdef statements

more ifdef

Update decode.cpp

Update decode.cpp

Update decode.cpp
 2025-01-14 21:29:47 -08:00
MichaelJSr
929ef1b6e2 Remove unused EXTV code, clean up code, pragma once around vpu.h 2025-01-13 16:45:13 -08:00
tinebp
6b23d290c3 vector ISA updates 2024-12-05 14:43:51 -08:00
MichaelJSr
073e0ddd10 Adds the riscv vector extension into simx 
Added vector regression test to ci.yml
 2024-11-27 23:22:22 -08:00
jaewon-lee-github
e5f2442353 Update Virtual Memory testing 2024-09-20 08:58:11 -04:00
Jaewon Lee
e91eb4aed4 merge from master branch 2024-09-12 10:32:02 -04:00
Hanran Wu
ea9560b33b merge 2024-08-23 17:44:24 -04:00
Blaise Tine
fc0392e5e3 fixed typo 2024-08-03 00:54:17 -07:00
Blaise Tine
3223a40a76 Verilator optimization flags update 2024-07-29 14:58:35 -07:00
Blaise Tine
75f1f957d4 minor updates 2024-07-29 03:28:51 -07:00
Blaise Tine
fb141ae522 Ramulator 2.0 with HBM 2.0 support 
Verilator 5.0 support
SimX C++17 requirement
 2024-07-21 06:57:13 -07:00
Blaise Tine
47d578c4d2 runtime refactoring 2024-05-27 18:55:42 -07:00
Blaise Tine
32f39264ef runtime dynamic loading for driver-specific implementations 2024-05-26 19:05:17 -07:00
Blaise Tine
6b81b26ffc enabling Makefile configuration with build folder support 2024-03-30 02:28:39 -07:00
Blaise Tine
402c911991 simx mem_coalescer 2024-03-24 20:31:36 -07:00
Blaise Tine
840ced22a9 simx refactoring - emulation vs simulation discrete separation 2024-03-12 00:23:42 -07:00
Blaise Tine
26d45ed9db renamed shared to local memory 2024-02-29 01:04:52 -08:00
Blaise Tine
7425446b15 fixed DESTDIR support in simumation Makefiles 2023-12-29 14:11:16 -08:00
Blaise Tine
e62d122c9b enabling temporary build directory for blackbox multiple instances 2023-12-28 20:06:10 -08:00
Blaise Tine
c7a81d1493 adding sockets support to simx and cache subsystem refactoring 
minor update

minor update

minor updates
 2023-12-20 15:16:12 -08:00
Blaise Tine
d47cccc157 Vortex 2.0 changes: 
+ Microarchitecture optimizations
+ 64-bit support
+ Xilinx FPGA support
+ LLVM-16 support
+ Refactoring and quality control fixes
 2023-10-19 20:51:22 -07:00
Santosh Srivatsan
b7e5a83ba3 Merged branch xlen-parameterization into staging 2022-02-05 13:47:42 -05:00
Blaise Tine
cf2a0a5f39 code refactoring 2022-02-04 00:07:24 -05:00
Blaise Tine
f7887d8720 refactoring device memory allocation and cleanup 2022-01-28 21:57:16 -05:00
Santosh Srivatsan
7aa93a735d Added FLEN parameterization for RV32/64 F and D instructions 2022-01-24 15:42:15 -05:00
Santosh Srivatsan
ad92c09f5b Changed all instances of DWord to XWord and DWordI to XWordI. Added XLEN parameterization to the simx Makefile 2022-01-22 13:47:44 -05:00
Santosh Srivatsan
5edb9098ce Merge branch 'simx64' 2021-12-10 21:48:29 -05:00
Santosh Srivatsan
e7bc436b52 Renamed simX to simx 2021-12-10 16:57:29 -05:00
Blaise Tine
b741807f8c using ramulator dram simulator 2021-12-06 01:22:45 -05:00
Blaise Tine
2a7a4df342 simx directory name fix 2021-11-30 07:17:58 -05:00
Renamed from sim/simX/Makefile (Browse further)