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2168 commits 27 branches 9 tags 1.6 GiB
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129 commits

Author SHA1 Message Date
Blaise Tine
f7887d8720 refactoring device memory allocation and cleanup 2022-01-28 21:57:16 -05:00
Blaise Tine
5825b7c15a dram simulator fix 2021-12-07 22:44:06 -05:00
Blaise Tine
b741807f8c using ramulator dram simulator 2021-12-06 01:22:45 -05:00
Blaise Tine
18762dffce fixes: texture unit mem access sometimes going to smem, bilinear texture filtering; new: cache req_id, 2021-11-24 00:00:17 -05:00
Blaise Tine
27a65fdee7 driver refactoring 2021-11-14 09:05:15 -05:00
Blaise Tine
9656779d48 minor update 2021-11-14 04:45:06 -05:00
Blaise Tine
b529f538b8 Makefile updates 2021-10-17 10:52:07 -07:00
Blaise Tine
549629440d minor update 2021-10-11 17:11:36 -04:00
Blaise Tine
28e26f3130 minor update 2021-10-09 13:19:46 -07:00
Blaise Tine
54bddeee9c simulation framework refactoring 2021-10-09 10:20:42 -04:00
Blaise Tine
9f34b2944c code refactoring for Vivado, sv2v, and yosys compatibility 2021-09-27 08:55:10 -04:00
Blaise Tine
18172fa611 AXI memory bus support 2021-09-10 01:36:01 -07:00
Blaise Tine
a60bfc5e01 extending tracing feature for advanced debugging 2021-08-15 05:10:46 -07:00
Blaise Tine
640c98a4e8 Reverting Verilator versionb support to v4.200 2021-08-14 00:45:56 -07:00
Blaise Tine
36d95fd892 automatic perf dump fix 2021-08-13 19:23:13 -07:00
Blaise Tine
3c43308e71 Makfile fixes for latest version of Verilator 2021-08-13 04:35:40 -07:00
Blaise Tine
4976a8c4f2 enabling automatic device cleanup for bad applications not releasing the device on exit 2021-08-12 20:06:51 -07:00
Blaise Tine
c331da5ff7 adding fast DPI implemntation of imul and idiv 2021-06-22 09:02:41 -07:00
Blaise Tine
3cc1190cd7 CSRs I/O refactoring 2021-06-11 03:08:07 -07:00
Blaise Tine
b3e54e66f8 fixed compiler warnings 2021-05-23 10:54:06 -07:00
Blaise Tine
95f057bc2e fpga build refactoring 2021-04-29 06:17:28 -07:00
Blaise Tine
8410c49f53 code refactoring: DRAM => MEM renaming 2021-04-26 00:58:48 -07:00
Blaise Tine
0615e7481a minor update 2021-04-24 03:06:24 -04:00
Blaise Tine
4cb98a25a7 enabling 128-bit dram bus 2021-04-24 00:31:27 -04:00
Blaise Tine
66ea340d05 Fix RAM memory deallocation 2021-03-09 01:52:56 -08:00
Blaise Tine
907e6868cd simx refactoring, fixed simple.hex, compatibility with rtlsim and vlsim complete, added to regression suite 2021-03-08 23:58:33 -08:00
Blaise Tine
062d02ddce Merge branch 'master' of https://github.gatech.edu/casl/Vortex 2021-03-04 20:51:03 -08:00
Blaise Tine
a8452483fe simX refactoring 2021-02-27 02:27:19 -08:00
Blaise Tine
6c1dc96626 simX refactoring + removed oldRTL + CSR updates 2021-02-06 12:52:54 -08:00
Blaise Tine
5419859281 fcvt fix 2021-01-25 02:22:00 -08:00
Blaise Tine
5c83c594c1 minor update 2021-01-07 17:25:59 -08:00
Blaise Tine
146c285aa0 minor update 2021-01-06 19:59:04 -08:00
Blaise Tine
2b8435471a speeding up simulation using dedicated full dpi-based FPU core 2021-01-06 18:44:06 -08:00
Blaise Tine
e4a00dd0d9 fixed loader script stack setup 2020-12-31 22:37:20 -05:00
Blaise Tine
703a861fe9 added support for write-through cache, removed cache snooping support 2020-12-23 23:51:02 -08:00
Blaise Tine
d5438fd591 merging perf counters 2020-12-08 21:02:39 -08:00
Xandy Liu
1595ff08e2 PERF pipeline stalls and cache 2020-12-08 01:14:41 -05:00
Blaise Tine
b85391389b rename MSRQ to MSHR 2020-11-28 17:32:00 -05:00
Blaise Tine
00d7473268 build warnings clean 2020-11-28 14:59:13 -05:00
Blaise Tine
461be0880d fixed FPU-CSR data dependence 2020-11-25 09:05:38 -08:00
Blaise Tine
c04d385641 minor update 2020-11-23 20:12:04 -08:00
Blaise Tine
20f22c7446 scope minor fix 2020-11-22 11:51:46 -08:00
Blaise Tine
1795980a52 L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization 2020-11-21 09:47:56 -08:00
Blaise Tine
34b650be94 fixed shared memory addressing critical path, fixed VX_fp_noncomp output bug 2020-11-17 00:27:24 -08:00
Blaise Tine
61add25d96 minor fix 2020-11-16 08:23:16 -08:00
Blaise Tine
77bca2deca constant integration updates 2020-11-16 02:39:53 -08:00
Blaise Tine
e946d976e7 constant integration updates 2020-11-15 08:44:57 -08:00
Blaise Tine
5d58bf3d11 fixed l3cache hang using memory arbiter in afu 2020-11-15 06:36:32 -08:00
Blaise Tine
ce95c40aee fixed redundant cache fills 2020-11-11 12:07:27 -05:00
Blaise Tine
5be1d85648 cache refactoring (fixed redundant fill requests, merged fill and writeback queues), optimized priority encoder, fixed crs cycles count 2020-11-02 01:50:12 -08:00