Commit graph

324 commits

Author SHA1 Message Date
Blaise Tine
dc18bfabb8 minor update - remove mshr data store 2021-01-30 06:40:48 -08:00
Blaise Tine
5419859281 fcvt fix 2021-01-25 02:22:00 -08:00
Blaise Tine
8775f63ec4 lkg build rollout with 16cores optimization on arria10 2021-01-24 16:49:22 -08:00
Blaise Tine
74a687e395 minor updates 2021-01-18 05:43:30 -08:00
Blaise Tine
b17f1109c6 minor updates 2021-01-18 04:34:34 -08:00
Blaise Tine
a7f6b9fffc minor updates 2021-01-17 18:18:05 -08:00
Blaise Tine
8b42393189 minor updates 2021-01-17 17:33:41 -08:00
Blaise Tine
a046bd7a73 cache pipeline optimization 2021-01-17 17:19:52 -08:00
Blaise Tine
ed216ab39d minor updates 2021-01-17 13:58:43 -08:00
Blaise Tine
a69ba5ad7b cache flush support 2021-01-17 05:50:29 -08:00
Blaise Tine
d4e7b28be8 cache refactoring 2021-01-17 00:18:56 -08:00
Blaise Tine
5b80484123 minor updates 2021-01-16 14:16:10 -08:00
Blaise Tine
a56ecb696d minor updates 2021-01-16 14:05:47 -08:00
Blaise Tine
4f26228d50 minor updates 2021-01-16 05:33:28 -08:00
Blaise Tine
fcbf57b66a specialized shared memory module 2021-01-16 04:41:58 -08:00
Blaise Tine
f146178c2d minor updates 2021-01-13 15:52:03 -08:00
Blaise Tine
0e1650e1c2 bank deadlock fix 2021-01-13 15:51:42 -08:00
Blaise Tine
79cc4d98e6 bank deadlock fix 2021-01-13 13:06:07 -08:00
Blaise Tine
464c4f4bd8 minor updates 2021-01-12 20:16:59 -08:00
Blaise Tine
b4b5d6f0ab minor updates 2021-01-12 15:19:38 -08:00
Blaise Tine
e770824d47 fixed afu cci write bug, fixed profile cache write miss bug, fixed bram byteenable inferance 2021-01-10 20:26:15 -08:00
Blaise Tine
06945533cf fixed l2/l3 caches related bugs 2021-01-09 16:32:55 -08:00
Blaise Tine
146c285aa0 minor update 2021-01-06 19:59:04 -08:00
Blaise Tine
2058718f0f minor updates 2021-01-06 07:18:14 -08:00
Blaise Tine
31ff70fd4e minor updates 2021-01-05 15:03:41 -08:00
Blaise Tine
846a4036d3 minor update 2021-01-05 05:46:20 -08:00
Blaise Tine
39bff921be cache bug fixes 2021-01-05 05:04:49 -08:00
Blaise Tine
762b8e2e3e fixed cache mshr critical path 2021-01-04 12:49:40 -05:00
Blaise Tine
4d55118545 cache pipeline optimization - moved tag access to stage0 2021-01-03 23:10:41 -05:00
Blaise Tine
9cef1aae04 cache fill response address is the mshr's top address, no need to store it 2021-01-03 00:57:24 -05:00
Blaise Tine
4815ab099c using single-port block ram for cache tags, restoring core reset signal 2021-01-02 19:53:41 -08:00
Blaise Tine
a825941f51 Merge branch 'master' of https://github.gatech.edu/casl/Vortex 2021-01-02 16:06:09 -05:00
Blaise Tine
2d69ca5d67 scratchpad optimization for stack access using custom bank offset aligned to stack size 2021-01-02 16:00:00 -05:00
Blaise Tine
93c36273fa minor update 2021-01-01 20:24:18 -08:00
Blaise Tine
b2cfde5d6d enabling shared memory back 2020-12-31 19:19:14 -08:00
Blaise Tine
abe32ed553 cache optimization - moved read requests to stage1 and eliminating stage3 2020-12-31 07:40:58 -08:00
Blaise Tine
d44144f72f FPU float<->int conversion optimization 2020-12-29 15:37:45 -08:00
Blaise Tine
b459192dec critical path optimization - fpga fmax @4c = ~212 mhz 2020-12-26 03:28:32 -08:00
Blaise Tine
3fdc49971c minor update 2020-12-24 09:22:44 -08:00
Blaise Tine
703a861fe9 added support for write-through cache, removed cache snooping support 2020-12-23 23:51:02 -08:00
Blaise Tine
d956e268b9 adding new performance counters (banks utilization and DRAM bus utilization) 2020-12-22 12:33:45 -08:00
Blaise Tine
4b7d871d62 allowing partial cache request submissions, io bus support broken 2020-12-21 03:53:13 -08:00
Blaise Tine
4bbd7bf408 performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies, 2020-12-19 02:45:06 -08:00
Blaise Tine
d81ce8b609 minor update 2020-12-09 00:57:31 -08:00
Blaise Tine
12f7fcfa75 adding missing files, buffering teh snoop forwarder 2020-12-09 00:24:32 -08:00
Blaise Tine
d5438fd591 merging perf counters 2020-12-08 21:02:39 -08:00
Blaise Tine
d5fa82f5e4 cache req datapath optimizations 2020-12-08 02:58:08 -08:00
Xandy Liu
1595ff08e2 PERF pipeline stalls and cache 2020-12-08 01:14:41 -05:00
Blaise Tine
268ad15098 minor update 2020-12-06 22:55:17 -08:00
Blaise Tine
d68b32cd60 minor update 2020-12-06 22:40:27 -08:00