24 commits

Author	SHA1	Message	Date
Blaise Tine	2d00cec9d3	minor update	2024-09-30 02:12:30 -07:00
Blaise Tine	60860ec684	minor update	2024-09-29 09:03:24 -07:00
Blaise Tine	87e613d29d	fixed XRT AFU deadlock on exit	2024-09-28 05:20:37 -07:00
Blaise Tine	a37309c6b0	xrtsim implementation	2024-09-19 04:24:20 -07:00
Blaise Tine	7823f5529c	minor update	2024-09-08 01:38:48 -07:00
Blaise Tine	8db77ea1cd	minor updates	2024-09-05 21:29:01 -07:00
Blaise Tine	fd5903fef1	minor update	2024-09-04 03:34:25 -07:00
Blaise Tine	50b12ef754	fixed memory block size configuration	2024-08-06 12:46:19 -07:00
Blaise Tine	75f1f957d4	minor updates	2024-07-29 03:28:51 -07:00
Blaise Tine	c8455eb562	minor update	2024-07-27 01:35:07 -07:00
Blaise Tine	3de14dd8bf	Verilator crash workaround	2024-07-24 16:09:27 -07:00
Blaise Tine	2773b87ae5	minor update	2024-07-24 15:38:49 -07:00
Blaise Tine	24e8e91a94	DramSim fix	2024-07-22 03:37:10 -07:00
Blaise Tine	527910b31e	regression fixes	2024-07-22 00:29:56 -07:00
Blaise Tine	fb141ae522	Ramulator 2.0 with HBM 2.0 support ... Verilator 5.0 support SimX C++17 requirement	2024-07-21 06:57:13 -07:00
Blaise Tine	0dbcddcb54	minor update	2024-07-14 03:12:30 -07:00
Blaise Tine	3efced37c5	trace INSTANCE_ID refactoring	2024-07-09 13:33:17 -07:00
Blaise Tine	f8ef570778	riscv tests refactoring	2024-05-28 10:46:31 -07:00
Blaise Tine	db0f0fd353	runtime API refactoring to support memory reservation and protection	2024-04-28 04:23:00 -07:00
Blaise Tine	d47cccc157	Vortex 2.0 changes: ... + Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes	2023-10-19 20:51:22 -07:00
Blaise Tine	dce5e79f65	toolchain update	2023-05-15 18:53:24 -04:00
Blaise Tine	a06812f93f	minor updates	2022-02-01 22:51:33 -05:00
Blaise Tine	5825b7c15a	dram simulator fix	2021-12-07 22:44:06 -05:00
Blaise Tine	b741807f8c	using ramulator dram simulator	2021-12-06 01:22:45 -05:00