| .. |
|
cache
|
synthesis fixes
|
2020-03-05 06:58:51 -05:00 |
|
compat
|
Make ALU div/mul pipelines longer and support logic element multiplication mode for better long pipeline performance
|
2020-02-22 20:16:13 -05:00 |
|
interfaces
|
L3 and CLUSTRING WORKS
|
2020-03-10 02:41:47 -07:00 |
|
modelsim
|
8Warp 32Threads for GTCAD synthesis
|
2019-11-21 23:51:11 -05:00 |
|
pipe_regs
|
synthesis fixes
|
2020-03-05 06:58:51 -05:00 |
|
quartus
|
Add power analysis Make target
|
2020-03-12 13:14:50 -04:00 |
|
shared_memory
|
fix shared mem ram inference
|
2020-02-20 15:59:23 -05:00 |
|
simulate
|
minor build fixes
|
2020-03-27 20:56:18 -04:00 |
|
unit_tests/generic_queue
|
fixed write logic in generic_queue_ll
|
2020-03-07 06:56:11 -05:00 |
|
VX_cache
|
Migrating fpga_synthesis_temp to main
|
2020-03-27 13:15:23 -07:00 |
|
.DS_Store
|
New RF with Evaluation
|
2019-09-11 01:04:23 -04:00 |
|
.gitignore
|
Generate define overrides based on env vars for C and Verilog.
|
2020-03-26 04:08:43 -04:00 |
|
byte_enabled_simple_dual_port_ram.v
|
synthesis fixes
|
2020-03-05 06:58:51 -05:00 |
|
gen_config.py
|
Generate define overrides based on env vars for C and Verilog.
|
2020-03-26 04:08:43 -04:00 |
|
Makefile
|
minor build fixes
|
2020-03-27 20:56:18 -04:00 |
|
Vortex.v
|
code refactoring
|
2020-03-26 03:20:46 -04:00 |
|
Vortex_SOC.v
|
code refactoring
|
2020-03-26 03:20:46 -04:00 |
|
VX_alu.v
|
fixed Modelsim build errors
|
2020-03-26 03:56:44 -04:00 |
|
VX_back_end.v
|
MULTICORE WITH L2 WORKING
|
2020-03-09 01:17:11 -07:00 |
|
VX_countones.v
|
Modelsim Makefile compile + simulate - DPI
|
2019-10-26 19:01:49 -04:00 |
|
VX_csr_data.v
|
MULTICORE WITH L2 WORKING
|
2020-03-09 01:17:11 -07:00 |
|
VX_csr_handler.v
|
New Warp Scheduler + VCD Enable
|
2019-09-15 00:12:41 -04:00 |
|
VX_csr_pipe.v
|
MULTICORE WITH L2 WORKING
|
2020-03-09 01:17:11 -07:00 |
|
VX_csr_wrapper.v
|
SystemVerilog tweaks to appease Quartus and make Quartus synthesis work
|
2020-01-24 06:10:24 -05:00 |
|
VX_decode.v
|
Added CSRs, some Load unit tests are failing
|
2020-02-17 22:22:27 -08:00 |
|
VX_define.v
|
Migrating fpga_synthesis_temp to main
|
2020-03-27 13:15:23 -07:00 |
|
VX_dmem_controller.v
|
L3 and CLUSTRING WORKS
|
2020-03-10 02:41:47 -07:00 |
|
VX_execute_unit.v
|
synthesis fixes
|
2020-03-05 06:58:51 -05:00 |
|
VX_fetch.v
|
Cache Working on Mem Copy
|
2020-03-08 01:55:15 -08:00 |
|
VX_front_end.v
|
Icache working
|
2020-03-08 13:59:35 -07:00 |
|
VX_generic_priority_encoder.v
|
synthesis fixes
|
2020-03-05 06:58:51 -05:00 |
|
VX_generic_queue.v
|
synthesis fixes
|
2020-03-05 06:58:51 -05:00 |
|
VX_generic_queue_ll.v
|
Add modified RTL files for parameterized builds with VX_define_synth.v
|
2020-03-20 04:04:15 -04:00 |
|
VX_generic_register.v
|
Fix for Single-Threaded
|
2020-03-22 14:44:46 -07:00 |
|
VX_generic_stack.v
|
synthesis fixes
|
2020-03-05 06:58:51 -05:00 |
|
VX_gpgpu_inst.v
|
Fix for Single-Threaded
|
2020-03-22 14:44:46 -07:00 |
|
VX_gpr.v
|
8Warp 32Threads for GTCAD synthesis
|
2019-11-21 23:51:11 -05:00 |
|
VX_gpr_stage.v
|
synthesis fixes
|
2020-03-05 06:58:51 -05:00 |
|
VX_gpr_wrapper.v
|
SystemVerilog tweaks to appease Quartus and make Quartus synthesis work
|
2020-01-24 06:10:24 -05:00 |
|
VX_icache_stage.v
|
MULTICORE WITH L2 WORKING
|
2020-03-09 01:17:11 -07:00 |
|
VX_inst_multiplex.v
|
Merge branch 'master' into fpga_synthesis
|
2020-02-18 03:34:38 -05:00 |
|
VX_lsu.v
|
Migrating fpga_synthesis_temp to main
|
2020-03-27 13:15:23 -07:00 |
|
VX_lsu_addr_gen.v
|
SystemVerilog tweaks to appease Quartus and make Quartus synthesis work
|
2020-01-24 06:10:24 -05:00 |
|
VX_priority_encoder.v
|
Modelsim basic sim
|
2019-10-26 00:34:57 -04:00 |
|
VX_priority_encoder_w_mask.v
|
Cleanup imports of VX_define
|
2020-02-04 10:57:32 -05:00 |
|
VX_scheduler.v
|
MULTICORE WITH L2 WORKING
|
2020-03-09 01:17:11 -07:00 |
|
VX_warp.v
|
Cleanup imports of VX_define
|
2020-02-04 10:57:32 -05:00 |
|
VX_warp_scheduler.v
|
Fix for Single-Threaded
|
2020-03-22 14:44:46 -07:00 |
|
VX_writeback.v
|
Add threaded -O3 build mode
|
2020-03-21 17:23:40 -04:00 |
