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serv

Verilog 0 0

SERV - The SErial RISC-V CPU

asic fpga risc-v verilog

Updated 2026-02-03 00:51:36 -07:00

picorv32

Verilog 0 0

PicoRV32 - A Size-Optimized RISC-V CPU

Updated 2024-06-17 00:20:13 -06:00