github-mirrors

piwigo

Dockerfile 0 0

hacktoberfest

Updated 2025-06-14 11:33:27 -04:00

VexRiscv

Assembly 0 0

A FPGA friendly 32 bit RISC-V CPU implementation

cpu fpga riscv soc softcore spinalhdl verilog vhdl

Updated 2025-06-08 13:29:41 -04:00

serv

Verilog 0 0

SERV - The SErial RISC-V CPU

asic fpga risc-v verilog

Updated 2025-06-05 02:56:43 -04:00

cva5

SystemVerilog 0 0

The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.

Updated 2025-05-15 18:28:34 -04:00

rogueserver

Go 0 0

Game server backend and API for PokéRogue

backend golang pokerogue server webserver

Updated 2025-04-27 12:03:34 -04:00

cve2

SystemVerilog 0 0

The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.

Updated 2025-04-10 08:06:34 -04:00

docker-pleroma

Elixir 0 0

Docker image for the Pleroma federated social network

Updated 2025-03-10 05:17:51 -04:00

Pebble

C 0 0

This is the latest version of the internal repository from Pebble Technology providing the software to run on Pebble watches. Proprietary source code has been removed from this repository and it will not compile as-is. This is for information only.

Updated 2025-02-25 14:02:51 -05:00

yuzu

C++ 0 0

Nintendo Switch emulator

emulation emulator switch c-plus-plus cpp

Updated 2025-02-06 09:52:53 -05:00

ryujinx

C# 1 0

Experimental Nintendo Switch Emulator written in C#

csharp dotnet dotnet-core emulation emulator switch

Updated 2025-02-06 09:52:03 -05:00

picorv32