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github-mirrors/ neorv32

VHDL 0 0

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

asip axi cpu embedded fpga microcontroller neorv32 on-chip-debbuger processor risc-v riscv rtl rtos rv32 safety soc soft-core system-on-chip verilog vhdl

Updated 2025-04-17 13:02:34 -04:00

github-mirrors/ harv

VHDL 0 0

HARV - HArdened Risc-V

fault-tolerance fpga processor reliability risc-v rv32i

Updated 2022-03-10 13:29:46 -05:00

github-mirrors/ maestro

VHDL 0 0

A 5 stage-pipeline RV32I implementation in VHDL

Updated 2020-03-12 20:45:17 -04:00