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intel
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package import refactor
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2021-04-03 11:54:53 -07:00 |
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lutrams
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typo fixed
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2021-11-16 14:34:48 -08:00 |
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xilinx
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package import refactor
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2021-04-03 11:54:53 -07:00 |
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addr_hash.sv
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package import refactor
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2021-04-03 11:54:53 -07:00 |
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alu_unit.sv
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minor const alu changes
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2021-10-08 16:24:43 -07:00 |
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amo_alu.sv
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resolved enum conflicts
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2021-10-27 16:01:21 -07:00 |
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avalon_master.sv
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package import refactor
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2021-04-03 11:54:53 -07:00 |
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axi_master.sv
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package import refactor
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2021-04-03 11:54:53 -07:00 |
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axi_to_arb.sv
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resolved enum conflicts
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2021-10-27 16:01:21 -07:00 |
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barrel_shifter.sv
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package import refactor
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2021-04-03 11:54:53 -07:00 |
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binary_occupancy.sv
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package import refactor
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2021-04-03 11:54:53 -07:00 |
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branch_comparator.sv
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decode and branch cleanup
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2021-06-03 18:55:30 -07:00 |
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branch_predictor.sv
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re-parameterization
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2021-07-27 14:37:43 -07:00 |
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branch_predictor_ram.sv
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package import refactor
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2021-04-03 11:54:53 -07:00 |
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branch_unit.sv
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first stage of exception redesign
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2021-11-16 21:30:15 -08:00 |
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byte_en_BRAM.sv
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updated vendor selection config
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2021-11-15 14:08:04 -08:00 |
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clz.sv
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Div improvements
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2021-03-29 10:45:40 -07:00 |
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csr_types.sv
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CSR input cleanup
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2021-10-22 20:33:55 -07:00 |
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csr_unit.sv
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register csr update
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2021-11-16 21:28:51 -08:00 |
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cycler.sv
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code cleanup
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2018-06-11 15:24:22 -07:00 |
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dbram.sv
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package import refactor
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2021-04-03 11:54:53 -07:00 |
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dcache.sv
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re-parameterization
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2021-07-27 14:37:43 -07:00 |
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ddata_bank.sv
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package import refactor
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2021-04-03 11:54:53 -07:00 |
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decode_and_issue.sv
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added exception_unit_table
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2021-11-22 16:47:48 -08:00 |
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div_core.sv
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div control signal cleanups
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2021-10-26 19:57:28 -07:00 |
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div_unit.sv
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div control signal cleanups
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2021-10-26 19:57:28 -07:00 |
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dtag_banks.sv
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re-parameterization
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2021-07-27 14:37:43 -07:00 |
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external_interfaces.sv
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l1 arbiter clean up
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2021-04-04 12:42:51 -07:00 |
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fetch.sv
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delay retire by one cycle
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2021-11-03 14:05:56 -07:00 |
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gc_unit.sv
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added exception_unit_table
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2021-11-22 16:47:48 -08:00 |
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ibram.sv
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package import refactor
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2021-04-03 11:54:53 -07:00 |
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icache.sv
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re-parameterization
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2021-07-27 14:37:43 -07:00 |
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illegal_instruction_checker.sv
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moved CSR legal addr checking
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2021-10-27 16:06:22 -07:00 |
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instruction_metadata_and_id_management.sv
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added exception_unit_table
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2021-11-22 16:47:48 -08:00 |
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interfaces.sv
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added registerfile bypass
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2021-11-15 14:02:49 -08:00 |
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itag_banks.sv
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re-parameterization
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2021-07-27 14:37:43 -07:00 |
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l1_arbiter.sv
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re-parameterization
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2021-07-27 14:37:43 -07:00 |
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lfsr.sv
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added reset param to lfsr
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2021-11-16 14:47:37 -08:00 |
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load_queue.sv
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lsq interface split
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2021-04-03 14:12:48 -07:00 |
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load_store_queue.sv
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re-parameterization
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2021-07-27 14:37:43 -07:00 |
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load_store_unit.sv
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first stage of exception redesign
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2021-11-16 21:30:15 -08:00 |
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mmu.sv
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package import refactor
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2021-04-03 11:54:53 -07:00 |
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mul_unit.sv
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package import refactor
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2021-04-03 11:54:53 -07:00 |
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one_hot_occupancy.sv
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package import refactor
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2021-04-03 11:54:53 -07:00 |
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one_hot_to_integer.sv
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package import refactor
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2021-04-03 11:54:53 -07:00 |
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placer_randomizer.sv
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helper for placement randomization
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2019-01-03 12:39:09 -08:00 |
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priority_encoder.sv
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tool compatability changes
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2021-10-07 17:11:11 -07:00 |
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ras.sv
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re-parameterization
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2021-07-27 14:37:43 -07:00 |
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reg_inuse.sv
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code cleanups
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2020-01-22 19:59:33 -08:00 |
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register_bank.sv
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Intel inferrence changes
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2021-04-03 14:33:45 -07:00 |
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register_file.sv
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added registerfile bypass
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2021-11-15 14:02:49 -08:00 |
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register_free_list.sv
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package import refactor
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2021-04-03 11:54:53 -07:00 |
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renamer.sv
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switch spec_table to 1w_mr lutram
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2021-11-15 21:35:13 -08:00 |
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riscv_types.sv
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resolved enum conflicts
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2021-10-27 16:01:21 -07:00 |
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set_clr_reg_with_rst.sv
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code cleanup: converted set/clr register usage into a module
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2020-04-02 15:32:02 -07:00 |
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shift_counter.sv
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package import refactor
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2021-04-03 11:54:53 -07:00 |
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store_queue.sv
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precompute store_queue full
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2021-10-27 17:13:22 -07:00 |
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tag_bank.sv
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minor cleanups
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2020-06-30 11:06:07 -07:00 |
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taiga.sv
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added exception_unit_table
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2021-11-22 16:47:48 -08:00 |
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taiga_config.sv
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first stage of exception redesign
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2021-11-16 21:30:15 -08:00 |
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taiga_fifo.sv
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added reset param to lfsr
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2021-11-16 14:47:37 -08:00 |
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taiga_types.sv
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added exception_unit_table
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2021-11-22 16:47:48 -08:00 |
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tlb_lut_ram.sv
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added reset param to lfsr
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2021-11-16 14:47:37 -08:00 |
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toggle_memory.sv
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switched toggle-mem to new lutram blocks
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2021-11-15 21:03:56 -08:00 |
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toggle_memory_set.sv
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added reset param to lfsr
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2021-11-16 14:47:37 -08:00 |
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wishbone_master.sv
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package import refactor
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2021-04-03 11:54:53 -07:00 |
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writeback.sv
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re-parameterization
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2021-07-27 14:37:43 -07:00 |
