Gchauvon
42aa48affd
Add Verdi option and memory preloading for VCS simulator ( #772 )
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* miss_handler.sv: critical_word signals connection explicit to compile with VCS
Signed-off-by: Guillaume Chauvon <guillaume.chauvon@thalesgroup.com>
* Makefile: add verdi support and move gen files to vcs_result directory
Signed-off-by: Guillaume Chauvon <guillaume.chauvon@thalesgroup.com>
* VCS-32 Preloading
Signed-off-by: Guillaume Chauvon <guillaume.chauvon@thalesgroup.com>
2021-12-03 19:16:38 +01:00
JeanRochCoulon
1094082d75
Makefile: Implement plateforms defined in cva6 specification ( #769 )
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* Makefile: Implement the plateforms defined in cva6 specification
target variable can take cv64a6_imacfd_sv39, cv32a6_imac_sv0,
cv32a6_imac_sv32, cv32a6_imacf_sv32
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* Fix plateform name: from imacfd to imafdc
from imacf to imafc
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
2021-11-26 10:39:08 +01:00
Luca Colagrande
725a662384
Mask non-enabled interrupts in WFI control ( #765 )
2021-11-23 09:14:26 +01:00
André Sintzoff
0a39a0525e
Flist.*: use lfsr.sv instead of lfsr_8bit.sv ( #763 )
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as such replacement was done in cache subsystem
with PR #690 (caf1872837
2021-10-22 10:07:58 +02:00
Gianmarco Ottavi
010eed815b
Fix branch prediction for compressed instruction with unaligned addresses ( #756 )
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Signed-off-by: Gianmarco Ottavi <gianmarco@openhwgroup.org>
Co-authored-by: Gianmarco Ottavi <gianmarco@openhwgroup.org>
2021-10-10 11:09:45 +02:00
Gianmarco Ottavi
56165adc82
Fix update of the BHT on correct not taken prediction ( #754 )
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* Fixed updates of the bht on correct not_taken prediction
Signed-off-by: Gianmarco Ottavi <gianmarco@openhwgroup.org>
* Update core/branch_unit.sv
* Update core/branch_unit.sv
Co-authored-by: Gianmarco Ottavi <gianmarco@openhwgroup.org>
Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
2021-10-10 11:06:23 +02:00
Gianmarco Ottavi
924ec9c2e0
Fix performance bug on calls via BTB ( #753 )
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Signed-off-by: Gianmarco Ottavi <gianmarco@openhwgroup.org>
Co-authored-by: Gianmarco Ottavi <gianmarco@openhwgroup.org>
2021-10-09 10:20:39 +02:00
Gianmarco Ottavi
a90348ba71
Fix per counters for second commit port ( #751 )
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Signed-off-by: Gianmarco Ottavi <gianmarco@openhwgroup.org>
Co-authored-by: Gianmarco Ottavi <gianmarco@openhwgroup.org>
2021-10-09 10:19:29 +02:00
André Sintzoff
fd8e971f1e
Clean-up flists ( #750 )
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Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
Co-authored-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
2021-10-09 10:17:39 +02:00
Moritz Schneider
464f1daf18
Fix PMPCFG csr read for 32bit configuration ( #734 )
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Fixes #733
Signed-off-by: Moritz Schneider <moritz.schneider@inf.ethz.ch>
2021-10-06 09:30:48 +02:00
胡波
5380030a9a
Fix widths in WT data cache ( #735 )
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width of wtag in wbuffer_t should be PLEN-3, or DCACHE_TAG_WIDTH+DCACHE_INDEX_WIDTH-3.
width of wbuffer_cmp_addr should be PLEN.
width of the second param of is_inside_*_regions should be 64bits.
2021-10-01 14:41:14 +02:00
Nils Wistoff
486d9dcbc8
mmu: Prevent elaboration of incompat MMU version ( #713 )
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Fix the VCS flow for 64-bit CVA6 by only adding compatible MMU
sources. For instance, `mmu_sv32` assumes `PLEN` > `VLEN`, which
is not the case for RV64.
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
2021-10-01 11:41:17 +02:00
André Sintzoff
6cd1cfe796
Fix build after mmu reorg ( #737 )
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* core/Flist.cv64a6_imafdc_sv39: remove MMU moved files
mmu.sv, ptw.sv, tlb.sv are now in core/mmu_sv39
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* core/Flist.cv32a6_imac_sv0: remove MMU commented files
mmu.sv, ptw.sv, tlb.sv are now in core/mmu_sv32
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
2021-10-01 11:39:45 +02:00
André Sintzoff
3ddf797e95
Re-organize CVA6 and APU ( #725 )
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* Initial repository re-organization (#662 )
Initial attempt to split core from APU.
Signed-off-by: MikeOpenHWGroup <mike@openhwgroup.org>
Co-authored-by: Jean-Roch Coulon <jean-roch.coulon@invia.fr>
Compile `corev_apu` (#667 )
* Makefile verilates corev_apu
* Cleanup README
* Fix URL to repo
* Cleaned-up Makefile verilates corev_apu
Signed-off-by: Mike Thompson <mike@openhwgroup.org>
Add extended verification support (#685 )
* Makefile, riscv_pkg.sv: Select C64A6 or CV32A6
according to variant variable
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* add RVFI tracer and debug support
New files: rvfi_pkg.sv, rvfi_tracer.sv, ariane_rvfi.pkg.sv
- RVFI ports are added to ariane module
- rvfi_tracer.sv is a module added in ariane-testharness.sv
- RVFI_TRACE enables RVFI trace generation
Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* Move example_tb from cva6 to core-v-verif project
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* Makefile: remove useless rule for vsim
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* Makefile: add timescale definition when vsim is used
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* Makefile: add vcs support (fix #570 )
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* rvfi_tracer.sv: fix compilation error raised by vcs
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* Makefile: use only 2 threads for verilator
when using 4 threads, tests from riscv-compliance and riscv-tests
test suite are randomly stucked with rv32ima configuration
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* Flist.cva6: cleanup for synthesis workflow
Thales synthesis workflow does not manage comments at end of lines
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* Support FPGA generation
- ariane_xilinx.sv: fix AXI bus expansion
- .gitignore, Makefile, run.tcl: fix paths
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* riscv-dbg: update to 989389b0 (to support 32-bit CVA6 debug)
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* Create cva6_config_pkg to setup 32- or 64-bit configuration
According to selected configuration, Makefile calls
cv32a6_imac_sv0_config_pkg.sv or cv64a6_imac_sv39_config_pkg.sv
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* Flist, ariane_wrapper.sv: add wrapper to expand rvfi and axi structures
needed for dc_shell
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* cv*a6_*_pkg.sv, riscv_pkg.sv: (Fix) Use the camel case for the localparams
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* riscv_pkg.sv: clean-up the cva6_config_pkg import
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* Makefile, ariane.sv: RVFI_TRACE define conditions RVFI port in ariane
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
Co-authored-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
* Add lfsr.sv to manifest
Signed-off-by: Mike Thompson <mike@openhwgroup.org>
* Directory re-organzation
* fpga/xilinx/xlnx_axi_dwidth_converter_dm_*: move files (#726 )
into the new file organisation
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
* move mmu_sv32 and mmu_sv39, move bootrom, update path (#729 )
Signed-off-by: sjthales <sebastien.jacq@thalesgroup.com>
Co-authored-by: Mike Thompson <mike@openhwgroup.org>
Co-authored-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
Co-authored-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
Co-authored-by: sébastien jacq <57099003+sjthales@users.noreply.github.com>
2021-09-24 17:21:19 +02:00
