Parametrise the AXI interface of CVA6. With this PR, both cache subsystems support variable AXI address widths. The write-through cache furthermore supports variable AXI data widths. Moreover, this PR includes a modular AXI testbench for the WT cache to test the introduced changes. The following configurations of the WT cache have been verified:
XLEN Cacheline Width AXI data width AXI address width
64 128 64 64
64 128 128 52
64 512 128 64
32 512 256 48
32 64 32 48
This PR does the following
1. Bump the filelist for OpenPiton for new directory layout
2. Remove AXI Interface for OpenPiton in the top level
3. Fix several issues in MMU discovered during address translation last year, the changes in core/mmu_sv39/mmu.sv are a joint effort between Jbalkind minho-pulp zarubaf niwis acostillado tianrui-wei
4. disable bitmanip by default
5. separate an ariane config package for openpiton synthesis. Some of the previous changes makes ariane too big for openpiton, so we need to revert these changes
6. Don't increase number of writeback ports (NR_WB_PORTS) when cvxif is not enabled
* compressed_decoder.sv: Fix of word L/S as per ISA spec v2.2.
* core/compressed_decoder.sv: Use word L/S patterns in FLW/FSW/FLWSP/FSWSP
expansions on RV32C.
* Add load and store information to RVFI
* Add rs1 and rs2 information to RVFI
* Condition rvfi mem and rs1/rs2 information generation by RVFI_MEM
This add-on is requested by ISACOV and test termination.
see The RISC-V Instruction Set Manual Volume II: Privileged Architecture
Version 20211203
3.1.1 Hardware Performance Monitor
All counters should be implemented, but a legal implementation is to make
both the counter and its corresponding event selector be read-only 0.
Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
unlike other instructions with minor opcode == PRIV,
SFENCE.VMA do not check for rs1 != 0.
Only check for rd !=0 to raise illegal instruction
Signed-off-by: Guillaume Chauvon <guillaume.chauvon@thalesgroup.com>
Fixes#906
According to the spec:
> If accessing pte violates a PMA or PMP check, raise an access-fault
> exception corresponding to the original access type.
Found by @Phantom1003 and @ProjectDimlight
Signed-off-by: Moritz Schneider <moritz.schneider@inf.ethz.ch>
* Add support for "high" counter CSRs in 32-bit mode
In 32bit mode MCYCLEH, MINSTRETH, CYCLEH, TIMEH and INSTRETH are
used to return the most significant 32-bit value of the counters
which are now always 64-bit wide.
Signed-off-by: Steffen Persvold <spersvold@gmail.com>
* Enable writing of MCYCLEH and MINSTRETH CSRs
Signed-off-by: Steffen Persvold <spersvold@gmail.com>
When a store-conditional fails due to a missing reservation,
by specification it must return a non-zero value.
Previously a value of 64'b1 was returned by the axi_adapter.
However, when an atop's address is non-64bit-aligned, the return data
has to be realigned. This realignment causes the lower half-word
being lost, and the return datum taking a value of '0.
This commit fixes the bug by returning {64{1'b1}} from the axi_adapter.
* wb_dcache: Forward "atomic transactions" to AXI
* Correct bugs
* Forward LR/SC atomics
* Fix CI
* miss_handler: Route AMO port through arbiter
* axi_adapter: Correct LOAD AMOs handling
Accept read data only after (or together) handshake on B channel
* Restore old ID
* Correct atop encodings
* Correct AMOs AXI ID
* Correct wb_dcache testbench
Previously not comparing AMOs at all! Due to amo_exp_resp being 'x
* Realign and sign extend 32b request rdata
* Use axi_pkg definitions for ATOPs encoding
* Remove whitespace
* wb_dcache: Style corrections
Co-authored-by: Florian Zaruba <florianzaruba@gmail.com>
Co-authored-by: Florian Zaruba <florianzaruba@gmail.com>
* Fix illegal write to PMPCFG
Reported by Flavien Solt (@flaviens)
Signed-off-by: Moritz Schneider <moritz.schneider@inf.ethz.ch>
* Cleanup CSR code for PMP
Signed-off-by: Moritz Schneider <moritz.schneider@inf.ethz.ch>
* Change questa version reference format
* bump common_cells to v1.23
* Bump axi to v0.31.0, replace axi_node with axi_xbar
* Bump register_interface for axi compatibility
* add prot signals to axi_lite for compatibility
* Add top hierarchy modification and rs3 for general purpose register file
* CVA6 core modifications to enable CoreV-eXtension-Interface feature
* Addition of an example coprocessor to use with CoreV-eXtension-Interface functionnalities on CVA6
* CoreV-eXtension-Interface available for FPGA
* Add work directories to gitignore
* Flist: fix cvxif files
* CVXIF: Modification and bugfix for cvxif feature
* CVXIF: simplify destination register feature
* Make 3rd read port on regfile configurable
* example_copro: use fifo_v3 instead of stream_fifo
* Makefile: compilation copro using defines
* ariane_pkg,riscv_pkg: add parameter to en/disable cvxif
* cva6.sv, ariane.sv: add hierarchy between ariane and cva6
* Clean Up code and typo
* CVXIF: moved combinatorial part to cvxif_fu module in ex_stage
* instr_decoder: rename instr predecoder and package
* Clean Up code and typo
* cvxif modification to follow style guideline
* issue_read_operands.sv: fix always_ff block for cvxif functionnal uni
