64 commits

Author	SHA1	Message	Date
Moritz Schneider	6044454a07	Fix index calculation for PMPCFG CSR write logic (#2330)	2024-07-05 22:56:27 +02:00
Asmaa Kassimi	67dba2cad3	condition csr_regfile.sv (#2310)	2024-07-05 14:14:01 +02:00
Asmaa Kassimi	ace1643e91	Add lambda function to sort lint summary according to severity (#2316)	2024-07-03 16:46:30 +02:00
Côme	ce1e889716	update expected area (#2299)	2024-06-28 15:02:58 +02:00
Cesar Fuguet	9df64701bd	Update submodule core/cache_subsystem/hpdcache (#2265)	2024-06-18 11:54:35 +02:00
JeanRochCoulon	cb6211bbb8	Remove cv32a6_embedded configuration (#2246)	2024-06-14 08:30:17 +02:00
AngelaGonzalezMarino	8164828913	Fix instruction realign when C extension is not used (#2241)	2024-06-13 11:17:25 +02:00
JeanRochCoulon	2266f75f2d	MTVAL is read-only zero when TvalEn = 0 (#2231)	2024-06-11 11:22:41 +02:00
JeanRochCoulon	7ccf82ce76	Add param to enable/disable Zihpm and Zicntr extensions for 65x (#2208)	2024-06-10 15:14:03 +02:00
Jalali	278649d3ed	Update coverage script after exclude HPDcache module (#2197)	2024-06-05 09:55:48 +02:00
Guillaume Chauvon	a5152b03a5	Add support for cv32a65x dedicated synthesis (#2178)	2024-06-04 10:58:09 +02:00
Jalali	8e2393db99	Add the capability to add functional coverage results into the dashboard (#2183)	2024-06-03 11:47:22 +02:00
Côme	93648e8cf7	Revert "Functional coverage report in CI (#2127)" (#2168) ... This reverts commit d4f984dbce.	2024-05-30 10:37:56 +02:00
Asmaa Kassimi	6164ecbae2	Create Spyglass CI job and add Spyglass folder to cva6 repository (#2131)	2024-05-24 14:16:15 +02:00
Jalali	26e6a8de4e	HOTFIX: update HVP & CC report script to solve an error in CC JOb (#2139)	2024-05-21 21:32:08 +02:00
Jalali	d4f984dbce	Functional coverage report in CI (#2127)	2024-05-17 22:58:52 +02:00
JeanRochCoulon	f4ec364bf4	Fix MIE CSR described in #2004 and #2008 Github issue (#2017)	2024-04-08 19:54:55 +02:00
valentinThomazic	5c7ddcbcc5	Fix log naming and dashboard improvements (#2001)	2024-04-03 18:03:47 +02:00
valentinThomazic	fd12ee596c	Add smoke-tests and fpga logs on dashboard (#1928)	2024-03-14 14:43:56 +01:00
André Sintzoff	8c2bbb0527	cva6.py: fix typos in displayed messages (#1906)	2024-03-08 14:01:19 +01:00
valentinThomazic	fb86e7a5ac	Mark job as failed when build fails (#1891)	2024-03-05 17:57:32 +01:00
Yannick Casamatta	1dec79464e	add csr in rvfi (#1833)	2024-02-24 00:10:23 +01:00
André Sintzoff	71f57a38c2	csr_regfile.sv: no MENVCFG[H], MCOUNTEREN when no User mode (fix #1843) (#1861)	2024-02-21 18:16:35 +01:00
JeanRochCoulon	de5d0d7ed4	cv32a65x (#1799)	2024-02-01 13:11:45 +01:00
Jalali	dc633a282c	report_benchmark.py: Detecting "mcycle" without CSR pseudo-code (#1786)	2024-01-26 14:26:03 +01:00
Guillaume Chauvon	fa101fae7a	Parameterize TVAL to reduce size in embedded (#1784)	2024-01-25 15:47:06 +01:00
Yannick Casamatta	0ce6b40b26	Remove all logic and sequential related to RVFI in CORE cva6 (#1762)	2024-01-18 22:51:10 +01:00
Gull Ahmed	8c14b6aa4a	resolving issue #1613 (#1714)	2023-12-17 17:59:22 +01:00
Côme	4e3f470a75	ci: report embedded CoreMark/MHz score (#1710)	2023-12-14 13:29:31 +01:00
AEzzejjari	738d53af1c	Code coverage: condition RTL With parameters (#1703)	2023-12-13 07:52:47 +01:00
JeanRochCoulon	d2453163eb	Update embedded config to improve trade-off performance gate count (#1701)	2023-12-12 18:43:09 +01:00
JeanRochCoulon	9f0e1b327d	Add 16 entry BHT in embedded configuration (#1658)	2023-11-28 06:14:11 +01:00
JeanRochCoulon	feda9ece82	Configure load to be wait state zero in embedded configuration (#1657)	2023-11-27 18:20:36 +01:00
Côme	d0cba61b16	ci(merge rep): prevent interpolation in commit msg (#1637)	2023-11-16 16:56:16 +01:00
Côme	168292364a	use embedded config to run coremark (#1602)	2023-11-07 14:06:10 +01:00
JeanRochCoulon	b7e936e754	Implement only 1 dcache_ctrl instances when ACC and MMU_PRESENT are disabled (#1594)	2023-11-05 23:37:42 +01:00
JeanRochCoulon	b6ff6887c7	[hot fix] Update expected gate count (#1590)	2023-11-03 08:06:51 +00:00
AEzzejjari	1faaec09bc	Code_coverage: condition RTL with the debug parameter (#1582)	2023-10-31 17:35:59 +01:00
AEzzejjari	4b67475fa4	Code_coverage: condition RTL with the S-MODE parameter (#1574)	2023-10-27 22:38:52 +02:00
AEzzejjari	29a3f14868	Code_coverage: Add conditions for the AMO Extension (#1554)	2023-10-19 22:08:40 +02:00
AEzzejjari	350408c1ac	Code_Coverage: Display the coverage score at the end of the code coverage job (#1526)	2023-10-12 06:38:53 +02:00
Côme	483b498486	Update area + widen valitidy window (#1524) ... Widen area validity window to ±500 gates	2023-10-11 08:13:22 +02:00
Côme	e8022778b7	ci: reorganize jobs (#1517)	2023-10-09 22:35:23 +02:00
Côme	130bc2fb31	ci: update expected area (#1516)	2023-10-09 21:38:25 +02:00
JeanRochCoulon	bb644bedbf	expected_synth.yml due to Zicond activation (#1494)	2023-10-03 06:24:43 +02:00
JeanRochCoulon	13f37033dc	Update expected_synth.yml (#1484) ... #1483 has reduced the gate count. this PR fixes it.	2023-09-28 07:11:45 +02:00
Fatima Saleem	e76eec7f25	Bypass misaligned address exception info in case of no MMU (#1457)	2023-09-21 10:05:20 +02:00
Côme	76c965320b	Heavy CI refactoring (#1455)	2023-09-19 19:40:41 +02:00
AEzzejjari	b952b0d7c3	Code_coverage: Add conditions for the FPU (#1442)	2023-09-19 18:24:40 +02:00
Côme	3b90bcf4aa	Update CI readme after merging cva6 and core-v-verif (#1390)	2023-09-13 16:15:41 +02:00