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Author	SHA1	Message	Date
andriami	59177e37d3	Reformat the ariane_pkg to fix synthesis crash (#1750) ... Modify ariane_pkg.sv following issue #1726.	2024-01-08 20:02:07 +01:00
dependabot[bot]	c430c6c34b	Bump verif/core-v-verif from 4da8b11 to dfa7c47 (#1747)	2024-01-05 17:45:39 +01:00
Jalali	4cd5c4a7e8	Add overflow counter test & fix reset value (#1746)	2024-01-05 13:29:48 +01:00
dependabot[bot]	cd0ade199c	Bump verif/core-v-verif from 18c9d28 to 4da8b11 (#1745)	2024-01-04 10:43:32 +01:00
valentinThomazic	706daa0a3b	removed the usage of install-cva6.sh and add setup-env.sh (#1741)	2024-01-03 13:42:23 +01:00
JeanRochCoulon	72b855672e	Fix inhibit impact on MCYCLE csr (#1743)	2024-01-03 12:20:07 +01:00
JeanRochCoulon	2708df998d	Rename cva6 (#1723)	2024-01-02 12:05:07 +01:00
valentinThomazic	4feab99254	Add prerequisites to README (#1738)	2023-12-27 16:36:23 +01:00
Jérôme Quévremont	6e79e20cc6	UM: Part number + reshuffled Zb* RV32/RV64 instructions (#1733)	2023-12-21 17:23:14 +01:00
Anouar	8aca3438ee	Added CSR covegroups for read and write operations, hvp updated accordantly (#1706)	2023-12-21 13:54:20 +01:00
Yaotian Liu	e6a0d9e06a	fix: extra space in command (#1730)	2023-12-21 06:29:52 +01:00
Jérôme Quévremont	5716b378da	Integrated Zb* in user manual (index.rst) (#1728)	2023-12-20 08:39:10 +01:00
Gull Ahmed	b3139eaae0	update Zb* docs (#1721)	2023-12-19 17:46:23 +01:00
Côme	2b33926900	fix: exception on misaligned branch if no RVC (#1719)	2023-12-19 10:03:11 +01:00
Jérôme Quévremont	4103b2ccdc	Changing part number in user manual (#1718)	2023-12-18 16:32:30 +01:00
Gull Ahmed	8c14b6aa4a	resolving issue #1613 (#1714)	2023-12-17 17:59:22 +01:00
Jérôme Quévremont	ad570000b3	Remove fixed-time division (ISA-110) (#1670) ... After further investigation, the feature is not needed for security application. For safety applications, variable-time division is only one of several sources of unpredictability and it does not make no real sense to fix it.	2023-12-15 14:52:10 +01:00
JeanRochCoulon	5e9cb5d64e	Designdoc (#1713) ... * rename csr files * Revisit the design specification skeleton	2023-12-15 14:51:32 +01:00
Florian Zaruba	344c1db4b8	Clarify pmpcfgX on illegal write combination (fixes #1694) (#1711)	2023-12-14 15:48:40 +01:00
Florian Zaruba	8146c96d86	csr: Implement menvcfg (#1653)	2023-12-14 15:25:38 +01:00
Côme	fab3255823	refactor(decoder): simplify interrupt indexing (#1709)	2023-12-14 14:36:17 +01:00
Côme	4e3f470a75	ci: report embedded CoreMark/MHz score (#1710)	2023-12-14 13:29:31 +01:00
Jérôme Quévremont	6e41bc8b52	Updated user manual to address several configuration (second pass) (#1696)	2023-12-13 10:10:31 +01:00
Jérôme Quévremont	98c776dc2d	Updated user manual to address several configuration (first pass) (#1685)	2023-12-13 10:08:40 +01:00
AEzzejjari	738d53af1c	Code coverage: condition RTL With parameters (#1703)	2023-12-13 07:52:47 +01:00
MarioOpenHWGroup	e5a0993ef9	Verilator Tandem Support (#1702)	2023-12-12 18:49:49 +01:00
JeanRochCoulon	d2453163eb	Update embedded config to improve trade-off performance gate count (#1701)	2023-12-12 18:43:09 +01:00
MarioOpenHWGroup	809bcf4ed0	Update verilator to v5.018 (#1699)	2023-12-12 14:02:59 +01:00
dependabot[bot]	d812c03712	Bump verif/core-v-verif from 6779193 to 76b887f (#1698)	2023-12-11 22:16:44 +01:00
Guillaume Chauvon	cef7e573c4	Set StallRandom I/O to 0 to gain performance on vcs-testharness bench (#1695)	2023-12-11 18:53:27 +01:00
André Sintzoff	a837e94eac	CONTRIBUTING.md: add verible-verilog-format (#1689)	2023-12-08 19:59:40 +01:00
valentinThomazic	61fb0cdd5c	set default NUM_JOBS value to be the same accross all scripts (#1688)	2023-12-08 16:57:46 +01:00
valentinThomazic	b6bd2a9583	Clean-up: removed wrong and now useless variable declaration in Makefile (#1686)	2023-12-08 15:59:55 +01:00
valentinThomazic	6da3f465dc	make the readme quickstart more user-friendly (#1684)	2023-12-07 16:50:49 +01:00
André Sintzoff	e5d86993df	alu.sv: verible format (#1683)	2023-12-07 16:07:34 +01:00
Jérôme Quévremont	559aa8f640	Replacing KDT with Chips JU logo (#1682)	2023-12-07 16:03:37 +01:00
Zbigniew Chamski	2745f3edcf	[GCC toolchain builder] Provide means of throttling parallel builds. (#1680)	2023-12-07 10:04:33 +01:00
Nils Wistoff	c0a30e1c85	miss_handler: Direct transition from FLUSH to AMO (#1679)	2023-12-06 17:53:57 +01:00
Jérôme Quévremont	683e5e8494	Fixed broken links (#1678)	2023-12-06 17:21:48 +01:00
Nils Wistoff	8ef0d66d65	cache_ctrl: Do not accept new request during flush (#1677)	2023-12-06 12:03:45 +01:00
Luca Valente	abf55c01af	Fix event tracing on more commit ports. (#1665)	2023-12-06 11:49:32 +01:00
Nils Wistoff	29eae1ca22	tech_cells_generic: Upgrade to v0.2.13 (#1676)	2023-12-06 11:16:58 +01:00
Cesar Fuguet	2cfa4e5a10	Update version of the HPDcache submodule (#1673)	2023-12-06 09:25:31 +01:00
JeanRochCoulon	9952bce6a6	Add embedded csr description and CSR table list (#1662)	2023-12-06 09:16:21 +01:00
AEzzejjari	cbd3e9fe19	Modify coding style to improve CC (#1672)	2023-12-05 14:51:23 +01:00
AEzzejjari	3720295bd3	Code_coverage: condition RTL with the IS_XLEN64 parameter (#1666)	2023-12-04 22:21:48 +01:00
Côme	c508a3dff5	ci: add Verible to GitHub Actions (#1669)	2023-12-04 11:16:58 +00:00
André Sintzoff	c51819dcbd	verible-verilog-format: apply it on core directory (#1668) ... using verible-v0.0-3430-g060bde0f/bin/verible-verilog-format with default configuration Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>	2023-12-04 11:16:35 +00:00
AEzzejjari	36c105a50d	Code_coverage: condition RTL with the AxiBurstWriteEn parameter (#1667)	2023-12-01 22:59:12 +01:00
André Sintzoff	a88385c4ce	verible-verilog-format: update to bypass verible limitations (#1664) ... using verible-v0.0-3422-g520ca4b9/bin/verible-verilog-format with default configuration	2023-12-01 08:30:08 +01:00