Cesar Fuguet
5de7c6003a
hpdcache: bump new version of the submodule ( #1845 )
2024-02-19 18:17:40 +01:00
AEzzejjari
5e80c104c9
AXI agent: Connect the the new AXI agent ( #1817 )
2024-02-18 23:31:44 +01:00
Cesar Fuguet
45ffb59980
fix: support of AMOs in cv32 configurations ( #1841 )
2024-02-18 23:30:41 +01:00
Jalali
3d7e417bce
Functional coverage : Add cross to illegal and exception coverage models ( #1839 )
2024-02-18 23:30:11 +01:00
JeanRochCoulon
b4c287a18e
Design Document, add ID_STAGE description ( #1832 )
2024-02-16 16:17:46 +01:00
Jalali
33a7a8207a
GEN_TESTS: Add --priv option to command generated tests ( #1831 )
2024-02-14 10:39:01 +01:00
Cesar Fuguet
00c0ff083a
hpdcache: bump new version of the submodule ( #1830 )
2024-02-13 18:19:16 +01:00
MarioOpenHWGroup
c7f0eaf0d8
Bump verif/core-v-verif from fd68dfd to c7d2077 ( #1828 )
2024-02-13 14:20:21 +01:00
Zbigniew Chamski
d48c4b5b4e
Fix waveform generation using vcs-uvm. Add waveforms section to README. ( #1827 )
2024-02-13 12:08:18 +01:00
Jalali
3599839d2e
Functional coverage : Fix illegal cover_group sampling ( #1825 )
2024-02-12 16:16:38 +01:00
JeanRochCoulon
0f2b137984
Populate instruction chapter in CV32A65X Design Document ( #1820 )
2024-02-12 09:58:02 +01:00
Nils Wistoff
6e8e2652b8
miss_handler: Fix AMO AXI ID mapping ( #1821 )
2024-02-09 23:14:47 +01:00
Jalali
5a9e1efd18
CVA6 HVP : MAP Illegal and exception covergroup into hvp ( #1819 )
2024-02-09 15:40:05 +01:00
Nils Wistoff
f5d5becfdd
cva6_config: Add ZiCondExtEn localparam in v configs ( #1801 )
2024-02-09 13:47:20 +01:00
Jérôme Quévremont
ef3bb06fbf
Adding configuration-specific CSR doc ( #1766 )
2024-02-09 13:39:48 +01:00
Jalali
22e9173b84
Functional coverage : Create Unmapped instruction and exceptions coverage models ( #1818 )
2024-02-09 11:31:15 +01:00
JeanRochCoulon
3f8649ec7e
Table builder for specification ( #1814 )
2024-02-08 10:54:47 +01:00
dependabot[bot]
e46baf6944
Bump verif/core-v-verif from aa5fe84 to fd68dfd ( #1813 )
2024-02-07 10:54:46 +01:00
Jalali
877a07c368
CVA6 HVP : Map ZCB instructions & remove DRET instruction ( #1812 )
2024-02-06 23:38:46 +01:00
JeanRochCoulon
9d0c700f42
port_builder generates the table of ports ( #1805 )
2024-02-06 12:06:13 +01:00
dependabot[bot]
0883882c3b
Bump verif/core-v-verif from 79d03a5 to aa5fe84 ( #1806 )
2024-02-05 23:37:08 +01:00
CoralieAllioux
48ea9a1675
[Bugfix hpdcache] axi struct usage ( #1802 )
2024-02-05 18:51:44 +01:00
JeanRochCoulon
42b21b8034
Configure icache with 2 ways in cv32a65x ( #1800 )
...
set 2 ways of 2048 bytes
2024-02-01 16:47:05 +01:00
JeanRochCoulon
de5d0d7ed4
cv32a65x ( #1799 )
2024-02-01 13:11:45 +01:00
JeanRochCoulon
5378031681
Fix HPDCache to make it functional when ways=2 ( #1744 )
2024-01-30 21:50:12 +01:00
JeanRochCoulon
56f6216430
Run simulation for embedded configuration ( #1798 )
2024-01-30 11:06:54 +01:00
dependabot[bot]
ae3a1ead28
Bump verif/core-v-verif from f17b93a to 79d03a5 ( #1797 )
2024-01-29 22:46:26 +01:00
dependabot[bot]
1e78cc8e6e
Bump verif/core-v-verif from 752e67f to f17b93a ( #1789 )
...
Bumps [verif/core-v-verif](https://github.com/openhwgroup/core-v-verif ) from `752e67f` to `f17b93a`.
- [Release notes](https://github.com/openhwgroup/core-v-verif/releases )
- [Commits](752e67f54c...f17b93a693
2024-01-26 16:44:56 +00:00
Jalali
c2d9d4b283
MTVAL : Remove MTVAL CSR from CVA6 UVM environment ( #1788 )
2024-01-26 16:47:15 +01:00
Jalali
179084315f
ISACOV : Update seq Directed test, and remove failing tests from regression ( #1787 )
2024-01-26 15:02:31 +01:00
Jalali
dc633a282c
report_benchmark.py: Detecting "mcycle" without CSR pseudo-code ( #1786 )
2024-01-26 14:26:03 +01:00
Guillaume Chauvon
fa101fae7a
Parameterize TVAL to reduce size in embedded ( #1784 )
2024-01-25 15:47:06 +01:00
Guillaume Chauvon
13a4a092ab
Check that User mode is enable to set MPP to U-mode ( fix #1756 ) ( #1781 )
2024-01-25 10:05:57 +01:00
Guillaume Chauvon
e0ca60169b
Fix path for vcs init_testharness.do ( #1780 )
2024-01-24 17:49:02 +01:00
Jalali
358a73a07d
Enable zcb extension into cva6 UVM env ( #1777 )
2024-01-24 15:37:18 +00:00
dependabot[bot]
6568b18a54
Bump verif/core-v-verif from 0ea56b3 to 752e67f ( #1776 )
2024-01-23 16:01:03 +01:00
Jalali
cabbaf690d
Exclude cva6_rvfi_combi module from Code coverage ( #1773 )
2024-01-22 17:16:02 +01:00
Côme
5742d2abc9
fix: add missing parameters in cva6_rvfi.sv ( #1771 )
2024-01-19 16:19:34 +00:00
Siris Li
ef5e378c93
Fix bug in install-spike.sh ( #1763 )
2024-01-18 23:32:32 +01:00
Yannick Casamatta
0ce6b40b26
Remove all logic and sequential related to RVFI in CORE cva6 ( #1762 )
2024-01-18 22:51:10 +01:00
MarioOpenHWGroup
8b6e8295f8
Add priv level to cva6.py and fix smoke-tests ( #1768 )
2024-01-17 23:14:19 +01:00
Michael Platzer
78111aa5eb
config_pkg/csr_regfile: Add PMP entry rst vals & RO option ( #1769 )
...
This commit adds three new fields to the `cva6_cfg_t` configuration
struct, which allows to specify reset values for the PMP configuration
and address CSRs as well as optionally making individual PMP entries
read-only. The purpose is to allow hard-wiring of certain regions'
privileges, which is explicitly allowed by the RISC-V Privileged
Architecture specification Machine-Level ISA, v1.12 (see Sect. 3.7).
2024-01-17 17:41:38 +01:00
Michael Platzer
37427a75a9
acc_dispatcher: Add ld/st priv mode, sum & PMP iface ( #1767 )
2024-01-17 00:43:21 +01:00
dependabot[bot]
284200dfc9
Bump verif/core-v-verif from dfa7c47 to 0ea56b3 ( #1764 )
2024-01-15 20:44:47 +01:00
Domenic Wüthrich
49cdc9045c
Break timing loop in axi adapter arbiter of WB cache ( #1761 )
2024-01-15 15:18:11 +01:00
André Sintzoff
3afe870d78
csr_regfile.sv: add RVB field for MISA ( fix #1734 ) ( #1760 )
2024-01-15 14:34:25 +01:00
Guillaume Chauvon
969c91eefa
Check that loaded elf segment does not overlap on last loaded address ( #1755 )
2024-01-11 11:37:00 +01:00
André Sintzoff
dc634c61de
doc: update MVENDORID CSR value ( fix #1735 ) ( #1753 )
2024-01-10 11:30:48 +01:00
JeanRochCoulon
88ab5a94dc
Update contibuting.md: contribution shall not impact code coverage ( #1752 )
2024-01-09 15:38:30 +01:00
Jalali
4279cc0f6e
Fix CSR coverage model & HVP ( #1751 )
2024-01-09 11:55:09 +01:00
