2 commits

Author	SHA1	Message	Date
Michael Schaffner	d30369da8a	fpu: Add distributed pipe regs to ease FPGA timing	2019-06-04 10:36:17 +02:00
Florian Zaruba	b1bdc0c02c	Add System Verilog FPU (#163) ... * Change reset strategy in ariane_verilog_wrap.sv, remove unneeded sigs in serpent_peripherals. * saving... * ⬆️ Updates for new FPU * Add sv fpu to FPGA flow * Use multi-threading capabilities of verilator - Deactivate non-standard floating point arguments - Make multi-threading conditional on the availability of verilator 4 * Remove DPI threadsafety * Reduce FPGA clock frequency - Remove couple of -v- tests to reduce test-time * Fix documentation and fpga flow - Fix cycle time to accommodate FPU - Fix FPGA constraints * Change UART frequency	2019-03-18 11:51:58 +01:00