khandelwaltanuj
3a389af151
added correct reset val ( #2823 )
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For cv64a60ax configuration
2025-03-12 15:19:15 +01:00
khandelwaltanuj
ab89beaebb
Adding a new configuration file for cv64a60ax and dv target RV64IMAFDC ( #2761 )
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A new configuration file and core v target is added to start working on a 64 bit CVA6 core.
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Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
2025-02-28 07:55:13 +01:00
Zbigniew Chamski
ed89c717f7
[CV32A65X] Update PMPADDRn spec to make bit 0 ROCST 0. Update config files. ( #2651 )
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Update CV32A65X-annotated privileged ISA specification to reflect the fact that with PMP granularity 8 and only supported PMP address matching modes being OFF and TOR, bit 0 of the pmpaddr0..pmpaddr7 registers can be safely made read-only zero. Update riscv-config specifications and its generated files accordingly.
2024-12-09 13:22:38 +01:00
Zbigniew Chamski
8a84f788d6
Increase Spike PMP granularity to 8. Update yaml spec files accordingly. ( #2624 )
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Update riscv-config spec files and Spike Yaml file for CV32A65X.
Bump CVV to change Spike default PMP granularity to 8 and to include corresponding Spike Yaml parameter.
2024-11-21 12:19:24 +01:00
Zbigniew Chamski
89eb77a249
[Spike tandem] Fix Yaml config files for CV32A65X. Fix Questa tandem. Add workaround for AXI end-of-test asserts. ( #2436 )
2024-08-19 11:09:32 +02:00
Zbigniew Chamski
4e9abb284c
[cv32a65x] Remove unsupported Zifencei from riscv-config ISA string. ( #2419 )
2024-07-30 09:20:33 +02:00
Zbigniew Chamski
8dcdf8fb56
[riscv-config] Add memory map entry to platform schema and to CV32A65X platform spec. ( #2411 )
2024-07-26 23:50:51 +02:00
Zbigniew Chamski
96b0508525
[riscv-config] Update PMP definitions in cv32q65x spec ( #2401 )
2024-07-25 22:06:51 +02:00
Zbigniew Chamski
17ea49439f
[riscv-config] Update riscv-config tool, CV32A65X specs and the rendering of CSRs. ( #2270 )
2024-06-19 12:08:15 +02:00
Zbigniew Chamski
592487ffa0
[riscv-config] Align CV32A65X spec on adoc, cleanup defs. Fix CSR updater. ( #2206 )
2024-06-06 11:19:41 +02:00
Zbigniew Chamski
aa76752f18
Update riscv-config infra to better match expressivity needs of CV32A65X. ( #2193 )
2024-06-04 18:12:14 +02:00
Zbigniew Chamski
c30c20bc2b
[riscv-config] HOTFIX: Regenerate output files for CV32A65X. ( #2176 )
2024-05-31 12:39:10 +02:00
Zbigniew Chamski
2534713373
[riscv-config] Fix issues in CV32A65X input spec and regenerate output. ( #2165 )
2024-05-29 17:35:47 +02:00
Zbigniew Chamski
2240bd079b
Add initial riscv-config input specs, validation harness and YAML outputs for CV32A65X. ( #2133 )
2024-05-21 07:21:57 +02:00
